From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 1A771212574; Thu, 25 Sep 2025 13:02:39 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758805360; cv=none; b=eypYditTe4qWxlJtu3jmzx9axkZmGd025Jh2PLFtDZQAMbWmHRI/5Tg1Gf8MLVw94oT/jyx0b9CjIsECOYvy+FlXehH6XCGT50WBrYbS+Udc4ruBz81tDCMSrSTg7nsHc2mKx77Ds0rET2RBbaZXYgtrW9spKW36u3Au6jukZhk= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758805360; c=relaxed/simple; bh=AfsLdojQ8QPIxkk+3F9A1jxrBChJ42VMetvVNH9c3ik=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=aPNVoqFTjzTGr8BahMcBUfN8fPoWfrT6n2ALFwogjxEwXV1+HecYYU5DwtaLLvGAK7tOBG6l5gFyVn3r5/UOKRhQIuJtlcl+SxQIRUdVWjMZJnEe0rJWdrf8GlINAMm9Gsx2e82qeiegdGLuIgtqkIVCs2yBNjoG3s773Z3kLN0= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=p3jedWCv; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="p3jedWCv" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 928E6C4CEF0; Thu, 25 Sep 2025 13:02:39 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758805359; bh=AfsLdojQ8QPIxkk+3F9A1jxrBChJ42VMetvVNH9c3ik=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=p3jedWCvT2s2T09odYijh9bcA9Md64UeMkYKOBHBiKJeSOJJGHdyILIeYXqDU32Sm EScE8ruuAuyPFrIbrQyYWyON3RSkCvn7ICDWNilOzchTFaKR5VYKAejBOskPSocCDI MeFGgCe61Ltm6fXOrXiqSeIu1zBs7QSkW9xYO+sC/x2mP9suyUuXzantX4ekWg/4UH eWQsEURzUjkVQ+dG1ltI4auEGz4ls1lNMxyk88CjeeiBxDCOr3ODJ/VElF8HgODxJm zIJ4jI6TCeLaWFoDKKfRj10nf13CnN1FzOb7HcnUbS2zXDjW96EaZfS5KfS24gz+Dn Zkuk5MLx3pW6A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v1lcL-00000009MWY-1N7B; Thu, 25 Sep 2025 13:02:37 +0000 Date: Thu, 25 Sep 2025 14:02:36 +0100 Message-ID: <867bxm1y8j.wl-maz@kernel.org> From: Marc Zyngier To: Pankaj Patil Cc: Bjorn Andersson , Konrad Dybcio , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 03/24] arm64: dts: qcom: Introduce Glymur base dtsi and CRD dts In-Reply-To: <20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com> References: <20250925-v3_glymur_introduction-v1-0-24b601bbecc0@oss.qualcomm.com> <20250925-v3_glymur_introduction-v1-3-24b601bbecc0@oss.qualcomm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: pankaj.patil@oss.qualcomm.com, andersson@kernel.org, konradybcio@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 25 Sep 2025 07:32:11 +0100, Pankaj Patil wrote: > > Introduce initial device tree support for Glymur - Qualcomm's > next-generation compute SoC and it's associated Compute Reference > Device (CRD) platform. > > The dt describes CPUs, CPU map, GCC and RPMHCC clock controllers, > geni UART, interrupt controller, TLMM, reserved memory, > interconnects, SMMU, firmware scm, watchdog, apps rsc, RPMHPD, > SRAM, PSCI and pmu nodes. > > Signed-off-by: Pankaj Patil > --- > arch/arm64/boot/dts/qcom/Makefile | 1 + > arch/arm64/boot/dts/qcom/glymur-crd.dts | 25 + > arch/arm64/boot/dts/qcom/glymur.dtsi | 1320 +++++++++++++++++++++++++++++++ > 3 files changed, 1346 insertions(+) > [...] > + intc: interrupt-controller@17000000 { > + compatible = "arm,gic-v3"; > + reg = <0x0 0x17000000 0x0 0x10000>, > + <0x0 0x17080000 0x0 0x480000>; > + > + interrupts = ; > + > + #interrupt-cells = <3>; > + interrupt-controller; > + > + #redistributor-regions = <1>; > + redistributor-stride = <0x0 0x40000>; Drop these two properties. I assume that your GIC implementation is compliant with the architecture, and doesn't need hand-holding. > + > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + gic_its: gic-its@17040000 { > + compatible = "arm,gic-v3-its"; > + reg = <0x0 0x17040000 0x0 0x40000>; > + > + msi-controller; > + #msi-cells = <1>; > + }; > + }; [...] > + timer { > + compatible = "arm,armv8-timer"; > + interrupts = , > + , > + , > + ; You are missing at one interrupt here, as the CPUs have both secure security state and FEAT_VHE (hint: the EL2 virtual timer also has an interrupt, usually on PPI 12). M. -- Without deviation from the norm, progress is not possible.