[PATCH 0/5] arm64/sysreg: Sort sysreg by encoding

[PATCH 0/5] arm64/sysreg: Sort sysreg by encoding

[James Clark]

A few small fixes and then sort and ensure sysreg remains sorted due to
the discussion here [1].

Applies to next-20250115 for the review but I can repost after rc1.

[1]: https://lore.kernel.org/all/996c7843-7f51-49a0-9122-e688e37f9902@sirena.org.uk/

James Clark (5):
  arm64/sysreg: Fix unbalanced closing block
  arm64/sysreg: Enforce whole line match for closing blocks
  arm64/sysreg: Enforce whole word for opening blocks
  arm64/sysreg: Sort sysreg by encoding
  arm64/sysreg: Enforce sorting

 arch/arm64/tools/gen-sysreg.awk |   36 +-
 arch/arm64/tools/sysreg         | 1010 +++++++++++++++----------------
 2 files changed, 526 insertions(+), 520 deletions(-)

-- 
2.34.1

[PATCH 1/5] arm64/sysreg: Fix unbalanced closing block

[James Clark]

This is a sysreg block so close it with one. This doesn't make a
difference to the output because the script only matches on the
beginning of the word to close blocks which is correct by coincidence
here.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 arch/arm64/tools/sysreg | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index 762ee084b37c..bbe7df69da9c 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -2074,7 +2074,7 @@ EndEnum
 Res0	4:2
 Field	1	ExTRE
 Field	0	E0TRE
-EndSysregFields
+EndSysreg
 
 Sysreg	SMPRI_EL1	3	0	1	2	4
 Res0	63:4
-- 
2.34.1

[PATCH 2/5] arm64/sysreg: Enforce whole line match for closing blocks

[James Clark]

Match on the whole line to prevent matching on prefixes like "Endsysreg"
vs "EndsysregFields". This could potentially make the script go wrong
in weird ways so make it fall through to the fatal unhandled statement
catcher if it doesn't fully match the current block.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 arch/arm64/tools/gen-sysreg.awk | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index 1a2afc9fdd42..7c7412adf90e 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -127,7 +127,7 @@ END {
 	next
 }
 
-/^EndSysregFields/ && block_current() == "SysregFields" {
+/^EndSysregFields$/ && block_current() == "SysregFields" {
 	if (next_bit > 0)
 		fatal("Unspecified bits in " reg)
 
@@ -177,7 +177,7 @@ END {
 	next
 }
 
-/^EndSysreg/ && block_current() == "Sysreg" {
+/^EndSysreg$/ && block_current() == "Sysreg" {
 	if (next_bit > 0)
 		fatal("Unspecified bits in " reg)
 
@@ -310,7 +310,7 @@ END {
 	next
 }
 
-/^EndEnum/ && block_current() == "Enum" {
+/^EndEnum$/ && block_current() == "Enum" {
 
 	field = null
 	msb = null
-- 
2.34.1

Re: [PATCH 2/5] arm64/sysreg: Enforce whole line match for closing blocks

[Mark Brown]

[-- Attachment #1: Type: text/plain, Size: 382 bytes --]

On Wed, Jan 15, 2025 at 01:42:54PM +0000, James Clark wrote:
> Match on the whole line to prevent matching on prefixes like "Endsysreg"
> vs "EndsysregFields". This could potentially make the script go wrong
> in weird ways so make it fall through to the fatal unhandled statement
> catcher if it doesn't fully match the current block.

Reviewed-by: Mark Brown <broonie@kernel.org>

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 488 bytes --]

Re: [PATCH 2/5] arm64/sysreg: Enforce whole line match for closing blocks

[Marc Zyngier]

On Wed, 15 Jan 2025 13:42:54 +0000,
James Clark <james.clark@linaro.org> wrote:
> 
> Match on the whole line to prevent matching on prefixes like "Endsysreg"
> vs "EndsysregFields". This could potentially make the script go wrong
> in weird ways so make it fall through to the fatal unhandled statement
> catcher if it doesn't fully match the current block.
> 
> Signed-off-by: James Clark <james.clark@linaro.org>
> ---
>  arch/arm64/tools/gen-sysreg.awk | 6 +++---
>  1 file changed, 3 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
> index 1a2afc9fdd42..7c7412adf90e 100755
> --- a/arch/arm64/tools/gen-sysreg.awk
> +++ b/arch/arm64/tools/gen-sysreg.awk
> @@ -127,7 +127,7 @@ END {
>  	next
>  }
>  
> -/^EndSysregFields/ && block_current() == "SysregFields" {
> +/^EndSysregFields$/ && block_current() == "SysregFields" {

The problem with this sort of things is that it will now fail with
trailing spaces, which is both counter-intuitive and pretty hard to
spot.

Why don't you simply match the field number, like you do in patch 3?

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH 2/5] arm64/sysreg: Enforce whole line match for closing blocks

[James Clark]

On 15/01/2025 2:17 pm, Marc Zyngier wrote:
> On Wed, 15 Jan 2025 13:42:54 +0000,
> James Clark <james.clark@linaro.org> wrote:
>>
>> Match on the whole line to prevent matching on prefixes like "Endsysreg"
>> vs "EndsysregFields". This could potentially make the script go wrong
>> in weird ways so make it fall through to the fatal unhandled statement
>> catcher if it doesn't fully match the current block.
>>
>> Signed-off-by: James Clark <james.clark@linaro.org>
>> ---
>>   arch/arm64/tools/gen-sysreg.awk | 6 +++---
>>   1 file changed, 3 insertions(+), 3 deletions(-)
>>
>> diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
>> index 1a2afc9fdd42..7c7412adf90e 100755
>> --- a/arch/arm64/tools/gen-sysreg.awk
>> +++ b/arch/arm64/tools/gen-sysreg.awk
>> @@ -127,7 +127,7 @@ END {
>>   	next
>>   }
>>   
>> -/^EndSysregFields/ && block_current() == "SysregFields" {
>> +/^EndSysregFields$/ && block_current() == "SysregFields" {
> 
> The problem with this sort of things is that it will now fail with
> trailing spaces, which is both counter-intuitive and pretty hard to
> spot.
> 
> Why don't you simply match the field number, like you do in patch 3?
> 
> 	M.
> 

The intention was to ensure that the end tokens were the only thing on 
the line (including whitespace). But yeah it is slightly inconsistent 
compared to start tokens because as you mention "$1 ==" allows both 
leading and trailing whitespace.

I'll change it to "$1 ==" for end tokens as well and then add 
expect_fields(1) which catches unexpected trailing stuff but has a 
better warning.

James

[PATCH 3/5] arm64/sysreg: Enforce whole word for opening blocks

[James Clark]

Similarly to the previous change, opening blocks can also match on words
with common prefixes. Fix it by ensuring the whole word matches. This
doesn't do much more than catch trailing typos.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 arch/arm64/tools/gen-sysreg.awk | 23 +++++++++++------------
 1 file changed, 11 insertions(+), 12 deletions(-)

diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index 7c7412adf90e..7f578216dc68 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -111,11 +111,10 @@ END {
 /^$/ { next }
 /^[\t ]*#/ { next }
 
-/^SysregFields/ && block_current() == "Root" {
+$1 == "SysregFields" && block_current() == "Root" {
 	block_push("SysregFields")
 
 	expect_fields(2)
-
 	reg = $2
 
 	res0 = "UL(0)"
@@ -145,7 +144,7 @@ END {
 	next
 }
 
-/^Sysreg/ && block_current() == "Root" {
+$1 == "Sysreg" && block_current() == "Root" {
 	block_push("Sysreg")
 
 	expect_fields(7)
@@ -206,7 +205,7 @@ END {
 
 # Currently this is effectivey a comment, in future we may want to emit
 # defines for the fields.
-(/^Fields/ || /^Mapping/) && block_current() == "Sysreg" {
+($1 == "Fields" || $1 == "Mapping") && block_current() == "Sysreg" {
 	expect_fields(2)
 
 	if (next_bit != 63)
@@ -224,7 +223,7 @@ END {
 }
 
 
-/^Res0/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "Res0" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	expect_fields(2)
 	parse_bitdef(reg, "RES0", $2)
 	field = "RES0_" msb "_" lsb
@@ -234,7 +233,7 @@ END {
 	next
 }
 
-/^Res1/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "Res1" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	expect_fields(2)
 	parse_bitdef(reg, "RES1", $2)
 	field = "RES1_" msb "_" lsb
@@ -244,7 +243,7 @@ END {
 	next
 }
 
-/^Unkn/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "Unkn" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	expect_fields(2)
 	parse_bitdef(reg, "UNKN", $2)
 	field = "UNKN_" msb "_" lsb
@@ -254,7 +253,7 @@ END {
 	next
 }
 
-/^Field/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "Field" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	expect_fields(3)
 	field = $3
 	parse_bitdef(reg, field, $2)
@@ -265,14 +264,14 @@ END {
 	next
 }
 
-/^Raz/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "Raz" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	expect_fields(2)
 	parse_bitdef(reg, field, $2)
 
 	next
 }
 
-/^SignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "SignedEnum" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	block_push("Enum")
 
 	expect_fields(3)
@@ -285,7 +284,7 @@ END {
 	next
 }
 
-/^UnsignedEnum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "UnsignedEnum" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	block_push("Enum")
 
 	expect_fields(3)
@@ -298,7 +297,7 @@ END {
 	next
 }
 
-/^Enum/ && (block_current() == "Sysreg" || block_current() == "SysregFields") {
+$1 == "Enum" && (block_current() == "Sysreg" || block_current() == "SysregFields") {
 	block_push("Enum")
 
 	expect_fields(3)
-- 
2.34.1

[PATCH 4/5] arm64/sysreg: Sort sysreg by encoding

[James Clark]

It's mostly been sorted by sysreg encoding, but not 100%. Sort it so
new entries can be added without wondering where to put them.

The following python script was used to sort, keeping the top level
SysregFields and comments next to their current Sysreg entries by
splitting on "EndSysreg":

  # cat arch/arm64/tools/sysreg | python3 sort.py > sorted-sysreg
  import sys, re
  def key(block):
          reg = r"\w+\s+(\d+)\s+(\d+)\s+(\d+)\s+(\d+)\s+(\d+)"
          match = re.search(reg, block)
          sort_val = ''.join(f"{int(n):02d}" for n in match.groups())
          return (sort_val, block)
  sysreg = sys.stdin.read().split("\nEndSysreg\n")[:-1]
  sysreg = sorted(sysreg, key=key)
  print("\nEndSysreg\n".join(sysreg) + "\nEndSysreg")

Tested by diffing sorted outputs:

  $ diff <(sort arch/arm64/include/generated/asm/sysreg-defs.h)  \
         <(sort before-sysreg-defs.h) -s

  Files /dev/fd/63 and /dev/fd/62 are identical

Signed-off-by: James Clark <james.clark@linaro.org>
---
 arch/arm64/tools/sysreg | 1006 +++++++++++++++++++--------------------
 1 file changed, 503 insertions(+), 503 deletions(-)

diff --git a/arch/arm64/tools/sysreg b/arch/arm64/tools/sysreg
index bbe7df69da9c..fe1c58367ceb 100644
--- a/arch/arm64/tools/sysreg
+++ b/arch/arm64/tools/sysreg
@@ -661,71 +661,71 @@ UnsignedEnum	3:0	SEVL
 EndEnum
 EndSysreg
 
-Sysreg ID_ISAR6_EL1	3	0	0	2	7
-Res0	63:28
-UnsignedEnum	27:24	I8MM
+Sysreg ID_MMFR4_EL1	3	0	0	2	6
+Res0	63:32
+UnsignedEnum	31:28	EVT
 	0b0000	NI
-	0b0001	IMP
+	0b0001	NO_TLBIS
+	0b0010	TLBIS
 EndEnum
-UnsignedEnum	23:20	BF16
+UnsignedEnum	27:24	CCIDX
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	19:16	SPECRES
+UnsignedEnum	23:20	LSM
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	15:12	SB
+UnsignedEnum	19:16	HPDS
+	0b0000	NI
+	0b0001	AA32HPD
+	0b0010	HPDS2
+EndEnum
+UnsignedEnum	15:12	CnP
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	11:8	FHM
+UnsignedEnum	11:8	XNX
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	7:4	DP
+UnsignedEnum	7:4	AC2
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	3:0	JSCVT
+UnsignedEnum	3:0	SpecSEI
 	0b0000	NI
 	0b0001	IMP
 EndEnum
 EndSysreg
 
-Sysreg ID_MMFR4_EL1	3	0	0	2	6
-Res0	63:32
-UnsignedEnum	31:28	EVT
-	0b0000	NI
-	0b0001	NO_TLBIS
-	0b0010	TLBIS
-EndEnum
-UnsignedEnum	27:24	CCIDX
+Sysreg ID_ISAR6_EL1	3	0	0	2	7
+Res0	63:28
+UnsignedEnum	27:24	I8MM
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	23:20	LSM
+UnsignedEnum	23:20	BF16
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	19:16	HPDS
+UnsignedEnum	19:16	SPECRES
 	0b0000	NI
-	0b0001	AA32HPD
-	0b0010	HPDS2
+	0b0001	IMP
 EndEnum
-UnsignedEnum	15:12	CnP
+UnsignedEnum	15:12	SB
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	11:8	XNX
+UnsignedEnum	11:8	FHM
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	7:4	AC2
+UnsignedEnum	7:4	DP
 	0b0000	NI
 	0b0001	IMP
 EndEnum
-UnsignedEnum	3:0	SpecSEI
+UnsignedEnum	3:0	JSCVT
 	0b0000	NI
 	0b0001	IMP
 EndEnum
@@ -2064,6 +2064,16 @@ Field	17:16	ZEN
 Res0	15:0
 EndSysreg
 
+SysregFields	ZCR_ELx
+Res0	63:9
+Raz	8:4
+Field	3:0	LEN
+EndSysregFields
+
+Sysreg ZCR_EL1	3	0	1	2	0
+Fields ZCR_ELx
+EndSysreg
+
 Sysreg	TRFCR_EL1	3	0	1	2	1
 Res0	63:7
 UnsignedEnum	6:5	TS
@@ -2081,16 +2091,6 @@ Res0	63:4
 Field	3:0	PRIORITY
 EndSysreg
 
-SysregFields	ZCR_ELx
-Res0	63:9
-Raz	8:4
-Field	3:0	LEN
-EndSysregFields
-
-Sysreg ZCR_EL1	3	0	1	2	0
-Fields ZCR_ELx
-EndSysreg
-
 SysregFields	SMCR_ELx
 Res0	63:32
 Field	31	FA64
@@ -2104,6 +2104,36 @@ Sysreg	SMCR_EL1	3	0	1	2	6
 Fields	SMCR_ELx
 EndSysreg
 
+SysregFields TTBRx_EL1
+Field	63:48	ASID
+Field	47:1	BADDR
+Field	0	CnP
+EndSysregFields
+
+Sysreg	TTBR0_EL1	3	0	2	0	0
+Fields	TTBRx_EL1
+EndSysreg
+
+Sysreg	TTBR1_EL1	3	0	2	0	1
+Fields	TTBRx_EL1
+EndSysreg
+
+Sysreg	TCR2_EL1	3	0	2	0	3
+Res0	63:16
+Field	15	DisCH1
+Field	14	DisCH0
+Res0	13:12
+Field	11	HAFT
+Field	10	PTTWI
+Res0	9:6
+Field	5	D128
+Field	4	AIE
+Field	3	POE
+Field	2	E0POE
+Field	1	PIE
+Field	0	PnCH
+EndSysreg
+
 SysregFields	GCSCR_ELx
 Res0	63:10
 Field	9	STREn
@@ -2149,31 +2179,6 @@ Sysreg	FAR_EL1	3	0	6	0	0
 Field	63:0	ADDR
 EndSysreg
 
-Sysreg	PMICNTR_EL0	3	3	9	4	0
-Field	63:0	ICNT
-EndSysreg
-
-Sysreg	PMICFILTR_EL0	3	3	9	6	0
-Res0	63:59
-Field	58	SYNC
-Field	57:56	VS
-Res0	55:32
-Field	31	P
-Field	30	U
-Field	29	NSK
-Field	28	NSU
-Field	27	NSH
-Field	26	M
-Res0	25
-Field	24	SH
-Field	23	T
-Field	22	RLK
-Field	21	RLU
-Field	20	RLH
-Res0	19:16
-Field	15:0	evtCount
-EndSysreg
-
 Sysreg	PMSCR_EL1	3	0	9	9	0
 Res0	63:8
 Field	7:6	PCT
@@ -2298,72 +2303,283 @@ Field	4	P
 Field	3:0	ALIGN
 EndSysreg
 
-Sysreg	PMUACR_EL1	3	0	9	14	4
-Res0	63:33
-Field	32	F0
-Field	31	C
-Field	30:0	P
+Sysreg	TRBLIMITR_EL1	3	0	9	11	0
+Field	63:12	LIMIT
+Res0	11:7
+Field	6	XE
+Field	5	nVM
+Enum	4:3	TM
+	0b00	STOP
+	0b01	IRQ
+	0b11	IGNR
+EndEnum
+Enum	2:1	FM
+	0b00	FILL
+	0b01	WRAP
+	0b11	CBUF
+EndEnum
+Field	0	E
 EndSysreg
 
-Sysreg	PMSELR_EL0	3	3	9	12	5
-Res0	63:5
-Field	4:0	SEL
+Sysreg	TRBPTR_EL1	3	0	9	11	1
+Field	63:0	PTR
 EndSysreg
 
-SysregFields	CONTEXTIDR_ELx
-Res0	63:32
-Field	31:0	PROCID
-EndSysregFields
-
-Sysreg	CONTEXTIDR_EL1	3	0	13	0	1
-Fields	CONTEXTIDR_ELx
+Sysreg	TRBBASER_EL1	3	0	9	11	2
+Field	63:12	BASE
+Res0	11:0
 EndSysreg
 
-Sysreg	RCWSMASK_EL1	3	0	13	0	3
-Field	63:0	RCWSMASK
+Sysreg	TRBSR_EL1	3	0	9	11	3
+Res0	63:56
+Field	55:32	MSS2
+Field	31:26	EC
+Res0	25:24
+Field	23	DAT
+Field	22	IRQ
+Field	21	TRG
+Field	20	WRAP
+Res0	19
+Field	18	EA
+Field	17	S
+Res0	16
+Field	15:0	MSS
 EndSysreg
 
-Sysreg	TPIDR_EL1	3	0	13	0	4
-Field	63:0	ThreadID
+Sysreg	TRBMAR_EL1	3	0	9	11	4
+Res0	63:12
+Enum	11:10	PAS
+	0b00	SECURE
+	0b01	NON_SECURE
+	0b10	ROOT
+	0b11	REALM
+EndEnum
+Enum	9:8	SH
+	0b00	NON_SHAREABLE
+	0b10	OUTER_SHAREABLE
+	0b11	INNER_SHAREABLE
+EndEnum
+Field	7:0	Attr
 EndSysreg
 
-Sysreg	RCWMASK_EL1	3	0	13	0	6
-Field	63:0	RCWMASK
+Sysreg	TRBTRG_EL1	3	0	9	11	6
+Res0	63:32
+Field	31:0	TRG
 EndSysreg
 
-Sysreg	SCXTNUM_EL1	3	0	13	0	7
-Field	63:0	SoftwareContextNumber
+Sysreg	TRBIDR_EL1	3	0	9	11	7
+Res0	63:12
+Enum	11:8	EA
+	0b0000	NON_DESC
+	0b0001	IGNORE
+	0b0010	SERROR
+EndEnum
+Res0	7:6
+Field	5	F
+Field	4	P
+Field	3:0	Align
 EndSysreg
 
-# The bit layout for CCSIDR_EL1 depends on whether FEAT_CCIDX is implemented.
-# The following is for case when FEAT_CCIDX is not implemented.
-Sysreg	CCSIDR_EL1	3	1	0	0	0
-Res0	63:32
-Unkn	31:28
-Field	27:13	NumSets
-Field	12:3	Associativity
-Field	2:0	LineSize
+Sysreg	PMUACR_EL1	3	0	9	14	4
+Res0	63:33
+Field	32	F0
+Field	31	C
+Field	30:0	P
 EndSysreg
 
-Sysreg	CLIDR_EL1	3	1	0	0	1
-Res0	63:47
-Field	46:33	Ttypen
-Field	32:30	ICB
-Field	29:27	LoUU
-Field	26:24	LoC
-Field	23:21	LoUIS
-Field	20:18	Ctype7
-Field	17:15	Ctype6
-Field	14:12	Ctype5
-Field	11:9	Ctype4
-Field	8:6	Ctype3
-Field	5:3	Ctype2
-Field	2:0	Ctype1
-EndSysreg
+SysregFields MAIR2_ELx
+Field	63:56	Attr7
+Field	55:48	Attr6
+Field	47:40	Attr5
+Field	39:32	Attr4
+Field	31:24	Attr3
+Field	23:16	Attr2
+Field	15:8	Attr1
+Field	7:0	Attr0
+EndSysregFields
 
-Sysreg	CCSIDR2_EL1	3	1	0	0	2
-Res0	63:24
-Field	23:0	NumSets
+Sysreg	MAIR2_EL1	3	0	10	2	1
+Fields	MAIR2_ELx
+EndSysreg
+
+SysregFields PIRx_ELx
+Field	63:60	Perm15
+Field	59:56	Perm14
+Field	55:52	Perm13
+Field	51:48	Perm12
+Field	47:44	Perm11
+Field	43:40	Perm10
+Field	39:36	Perm9
+Field	35:32	Perm8
+Field	31:28	Perm7
+Field	27:24	Perm6
+Field	23:20	Perm5
+Field	19:16	Perm4
+Field	15:12	Perm3
+Field	11:8	Perm2
+Field	7:4	Perm1
+Field	3:0	Perm0
+EndSysregFields
+
+Sysreg	PIRE0_EL1	3	0	10	2	2
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIR_EL1		3	0	10	2	3
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	POR_EL1		3	0	10	2	4
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	S2POR_EL1	3	0	10	2	5
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	AMAIR2_EL1	3	0	10	3	1
+Field	63:0	ImpDef
+EndSysreg
+
+Sysreg	LORSA_EL1	3	0	10	4	0
+Res0	63:52
+Field	51:16	SA
+Res0	15:1
+Field	0	Valid
+EndSysreg
+
+Sysreg	LOREA_EL1	3	0	10	4	1
+Res0	63:52
+Field	51:48	EA_51_48
+Field	47:16	EA_47_16
+Res0	15:0
+EndSysreg
+
+Sysreg	LORN_EL1	3	0	10	4	2
+Res0	63:8
+Field	7:0	Num
+EndSysreg
+
+Sysreg	LORC_EL1	3	0	10	4	3
+Res0	63:10
+Field	9:2	DS
+Res0	1
+Field	0	EN
+EndSysreg
+
+Sysreg	MPAMIDR_EL1	3	0	10	4	4
+Res0	63:62
+Field	61	HAS_SDEFLT
+Field	60	HAS_FORCE_NS
+Field	59	SP4
+Field	58	HAS_TIDR
+Field	57	HAS_ALTSP
+Res0	56:40
+Field	39:32	PMG_MAX
+Res0	31:21
+Field	20:18	VPMR_MAX
+Field	17	HAS_HCR
+Res0	16
+Field	15:0	PARTID_MAX
+EndSysreg
+
+Sysreg	LORID_EL1	3	0	10	4	7
+Res0	63:24
+Field	23:16	LD
+Res0	15:8
+Field	7:0	LR
+EndSysreg
+
+Sysreg	MPAM1_EL1	3	0	10	5	0
+Field	63	MPAMEN
+Res0	62:61
+Field	60 FORCED_NS
+Res0	59:55
+Field	54	ALTSP_FRCD
+Res0	53:48
+Field	47:40	PMG_D
+Field	39:32	PMG_I
+Field	31:16	PARTID_D
+Field	15:0	PARTID_I
+EndSysreg
+
+Sysreg	MPAM0_EL1	3	0	10	5	1
+Res0	63:48
+Field	47:40	PMG_D
+Field	39:32	PMG_I
+Field	31:16	PARTID_D
+Field	15:0	PARTID_I
+EndSysreg
+
+Sysreg	ISR_EL1	3	0	12	1	0
+Res0	63:11
+Field	10	IS
+Field	9	FS
+Field	8	A
+Field	7	I
+Field	6	F
+Res0	5:0
+EndSysreg
+
+Sysreg	ICC_NMIAR1_EL1	3	0	12	9	5
+Res0	63:24
+Field	23:0	INTID
+EndSysreg
+
+SysregFields	CONTEXTIDR_ELx
+Res0	63:32
+Field	31:0	PROCID
+EndSysregFields
+
+Sysreg	CONTEXTIDR_EL1	3	0	13	0	1
+Fields	CONTEXTIDR_ELx
+EndSysreg
+
+Sysreg	RCWSMASK_EL1	3	0	13	0	3
+Field	63:0	RCWSMASK
+EndSysreg
+
+Sysreg	TPIDR_EL1	3	0	13	0	4
+Field	63:0	ThreadID
+EndSysreg
+
+Sysreg	RCWMASK_EL1	3	0	13	0	6
+Field	63:0	RCWMASK
+EndSysreg
+
+Sysreg	SCXTNUM_EL1	3	0	13	0	7
+Field	63:0	SoftwareContextNumber
+EndSysreg
+
+# The bit layout for CCSIDR_EL1 depends on whether FEAT_CCIDX is implemented.
+# The following is for case when FEAT_CCIDX is not implemented.
+Sysreg	CCSIDR_EL1	3	1	0	0	0
+Res0	63:32
+Unkn	31:28
+Field	27:13	NumSets
+Field	12:3	Associativity
+Field	2:0	LineSize
+EndSysreg
+
+Sysreg	CLIDR_EL1	3	1	0	0	1
+Res0	63:47
+Field	46:33	Ttypen
+Field	32:30	ICB
+Field	29:27	LoUU
+Field	26:24	LoC
+Field	23:21	LoUIS
+Field	20:18	Ctype7
+Field	17:15	Ctype6
+Field	14:12	Ctype5
+Field	11:9	Ctype4
+Field	8:6	Ctype3
+Field	5:3	Ctype2
+Field	2:0	Ctype1
+EndSysreg
+
+Sysreg	CCSIDR2_EL1	3	1	0	0	2
+Res0	63:24
+Field	23:0	NumSets
 EndSysreg
 
 Sysreg	GMID_EL1	3	1	0	0	4
@@ -2448,6 +2664,40 @@ UnsignedEnum	2:0	F8S1
 EndEnum
 EndSysreg
 
+Sysreg	PMICNTR_EL0	3	3	9	4	0
+Field	63:0	ICNT
+EndSysreg
+
+Sysreg	PMICFILTR_EL0	3	3	9	6	0
+Res0	63:59
+Field	58	SYNC
+Field	57:56	VS
+Res0	55:32
+Field	31	P
+Field	30	U
+Field	29	NSK
+Field	28	NSU
+Field	27	NSH
+Field	26	M
+Res0	25
+Field	24	SH
+Field	23	T
+Field	22	RLK
+Field	21	RLU
+Field	20	RLH
+Res0	19:16
+Field	15:0	evtCount
+EndSysreg
+
+Sysreg	PMSELR_EL0	3	3	9	12	5
+Res0	63:5
+Field	4:0	SEL
+EndSysreg
+
+Sysreg	POR_EL0		3	3	10	2	4
+Fields	PIRx_ELx
+EndSysreg
+
 SysregFields	HFGxTR_EL2
 Field	63	nAMAIR2_EL1
 Field	62	nMAIR2_EL1
@@ -2625,6 +2875,10 @@ Field	1	ICIALLU
 Field	0	ICIALLUIS
 EndSysreg
 
+Sysreg	ZCR_EL2	3	4	1	2	0
+Fields	ZCR_ELx
+EndSysreg
+
 Sysreg TRFCR_EL2	3	4	1	2	1
 Res0	63:7
 UnsignedEnum	6:5	TS
@@ -2640,18 +2894,114 @@ Field	1	E2TRE
 Field	0	E0HTRE
 EndSysreg
 
+Sysreg	HCRX_EL2	3	4	1	2	2
+Res0	63:25
+Field	24	PACMEn
+Field	23	EnFPM
+Field	22	GCSEn
+Field	21	EnIDCP128
+Field	20	EnSDERR
+Field	19	TMEA
+Field	18	EnSNERR
+Field	17	D128En
+Field	16	PTTWI
+Field	15	SCTLR2En
+Field	14	TCR2En
+Res0	13:12
+Field	11	MSCEn
+Field	10	MCE2
+Field	9	CMOW
+Field	8	VFNMI
+Field	7	VINMI
+Field	6	TALLINT
+Field	5	SMPME
+Field	4	FGTnXS
+Field	3	FnXS
+Field	2	EnASR
+Field	1	EnALS
+Field	0	EnAS0
+EndSysreg
 
-Sysreg HDFGRTR_EL2	3	4	3	1	4
-Field	63	PMBIDR_EL1
-Field	62	nPMSNEVFR_EL1
-Field	61	nBRBDATA
-Field	60	nBRBCTL
-Field	59	nBRBIDR
-Field	58	PMCEIDn_EL0
-Field	57	PMUSERENR_EL0
-Field	56	TRBTRG_EL1
-Field	55	TRBSR_EL1
-Field	54	TRBPTR_EL1
+Sysreg	SMPRIMAP_EL2	3	4	1	2	5
+Field	63:60	P15
+Field	59:56	P14
+Field	55:52	P13
+Field	51:48	P12
+Field	47:44	P11
+Field	43:40	P10
+Field	39:36	F9
+Field	35:32	P8
+Field	31:28	P7
+Field	27:24	P6
+Field	23:20	P5
+Field	19:16	P4
+Field	15:12	P3
+Field	11:8	P2
+Field	7:4	P1
+Field	3:0	P0
+EndSysreg
+
+Sysreg	SMCR_EL2	3	4	1	2	6
+Fields	SMCR_ELx
+EndSysreg
+
+Sysreg	TCR2_EL2	3	4	2	0	3
+Res0	63:16
+Field	15	DisCH1
+Field	14	DisCH0
+Field	13	AMEC1
+Field	12	AMEC0
+Field	11	HAFT
+Field	10	PTTWI
+Res0	9:6
+Field	5	D128
+Field	4	AIE
+Field	3	POE
+Field	2	E0POE
+Field	1	PIE
+Field	0	PnCH
+EndSysreg
+
+Sysreg	GCSCR_EL2	3	4	2	5	0
+Fields	GCSCR_ELx
+EndSysreg
+
+Sysreg	GCSPR_EL2	3	4	2	5	1
+Fields	GCSPR_ELx
+EndSysreg
+
+Sysreg	DACR32_EL2	3	4	3	0	0
+Res0	63:32
+Field	31:30	D15
+Field	29:28	D14
+Field	27:26	D13
+Field	25:24	D12
+Field	23:22	D11
+Field	21:20	D10
+Field	19:18	D9
+Field	17:16	D8
+Field	15:14	D7
+Field	13:12	D6
+Field	11:10	D5
+Field	9:8	D4
+Field	7:6	D3
+Field	5:4	D2
+Field	3:2	D1
+Field	1:0	D0
+EndSysreg
+
+
+Sysreg HDFGRTR_EL2	3	4	3	1	4
+Field	63	PMBIDR_EL1
+Field	62	nPMSNEVFR_EL1
+Field	61	nBRBDATA
+Field	60	nBRBCTL
+Field	59	nBRBIDR
+Field	58	PMCEIDn_EL0
+Field	57	PMUSERENR_EL0
+Field	56	TRBTRG_EL1
+Field	55	TRBSR_EL1
+Field	54	TRBPTR_EL1
 Field	53	TRBMAR_EL1
 Field	52	TRBLIMITR_EL1
 Field	51	TRBIDR_EL1
@@ -2813,89 +3163,6 @@ Field	1	AMEVCNTR00_EL0
 Field	0	AMCNTEN0
 EndSysreg
 
-Sysreg	ZCR_EL2	3	4	1	2	0
-Fields	ZCR_ELx
-EndSysreg
-
-Sysreg	HCRX_EL2	3	4	1	2	2
-Res0	63:25
-Field	24	PACMEn
-Field	23	EnFPM
-Field	22	GCSEn
-Field	21	EnIDCP128
-Field	20	EnSDERR
-Field	19	TMEA
-Field	18	EnSNERR
-Field	17	D128En
-Field	16	PTTWI
-Field	15	SCTLR2En
-Field	14	TCR2En
-Res0	13:12
-Field	11	MSCEn
-Field	10	MCE2
-Field	9	CMOW
-Field	8	VFNMI
-Field	7	VINMI
-Field	6	TALLINT
-Field	5	SMPME
-Field	4	FGTnXS
-Field	3	FnXS
-Field	2	EnASR
-Field	1	EnALS
-Field	0	EnAS0
-EndSysreg
-
-Sysreg	SMPRIMAP_EL2	3	4	1	2	5
-Field	63:60	P15
-Field	59:56	P14
-Field	55:52	P13
-Field	51:48	P12
-Field	47:44	P11
-Field	43:40	P10
-Field	39:36	F9
-Field	35:32	P8
-Field	31:28	P7
-Field	27:24	P6
-Field	23:20	P5
-Field	19:16	P4
-Field	15:12	P3
-Field	11:8	P2
-Field	7:4	P1
-Field	3:0	P0
-EndSysreg
-
-Sysreg	SMCR_EL2	3	4	1	2	6
-Fields	SMCR_ELx
-EndSysreg
-
-Sysreg	GCSCR_EL2	3	4	2	5	0
-Fields	GCSCR_ELx
-EndSysreg
-
-Sysreg	GCSPR_EL2	3	4	2	5	1
-Fields	GCSPR_ELx
-EndSysreg
-
-Sysreg	DACR32_EL2	3	4	3	0	0
-Res0	63:32
-Field	31:30	D15
-Field	29:28	D14
-Field	27:26	D13
-Field	25:24	D12
-Field	23:22	D11
-Field	21:20	D10
-Field	19:18	D9
-Field	17:16	D8
-Field	15:14	D7
-Field	13:12	D6
-Field	11:10	D5
-Field	9:8	D4
-Field	7:6	D3
-Field	5:4	D2
-Field	3:2	D1
-Field	1:0	D0
-EndSysreg
-
 Sysreg	FAR_EL2	3	4	6	0	0
 Field	63:0	ADDR
 EndSysreg
@@ -2915,6 +3182,30 @@ Field	1	E2SPE
 Field	0	E0HSPE
 EndSysreg
 
+Sysreg	MAIR2_EL2	3	4	10	1	1
+Fields	MAIR2_ELx
+EndSysreg
+
+Sysreg	PIRE0_EL2	3	4	10	2	2
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	PIR_EL2		3	4	10	2	3
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	POR_EL2		3	4	10	2	4
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	S2PIR_EL2	3	4	10	2	5
+Fields	PIRx_ELx
+EndSysreg
+
+Sysreg	AMAIR2_EL2	3	4	10	3	1
+Field	63:0	ImpDef
+EndSysreg
+
 Sysreg	MPAMHCR_EL2	3	4	10	4	0
 Res0	63:32
 Field	31	TRAP_MPAMIDR_EL1
@@ -3059,6 +3350,10 @@ Sysreg	SMCR_EL12	3	5	1	2	6
 Mapping	SMCR_EL1
 EndSysreg
 
+Sysreg	TCR2_EL12	3	5	2	0	3
+Mapping	TCR2_EL1
+EndSysreg
+
 Sysreg	GCSCR_EL12	3	5	2	5	0
 Mapping	GCSCR_EL1
 EndSysreg
@@ -3071,317 +3366,22 @@ Sysreg	FAR_EL12	3	5	6	0	0
 Field	63:0	ADDR
 EndSysreg
 
-Sysreg	MPAM1_EL12	3	5	10	5	0
-Fields	MPAM1_ELx
-EndSysreg
-
-Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
-Mapping	CONTEXTIDR_EL1
-EndSysreg
-
-SysregFields TTBRx_EL1
-Field	63:48	ASID
-Field	47:1	BADDR
-Field	0	CnP
-EndSysregFields
-
-Sysreg	TTBR0_EL1	3	0	2	0	0
-Fields	TTBRx_EL1
-EndSysreg
-
-Sysreg	TTBR1_EL1	3	0	2	0	1
-Fields	TTBRx_EL1
-EndSysreg
-
-Sysreg	TCR2_EL1	3	0	2	0	3
-Res0	63:16
-Field	15	DisCH1
-Field	14	DisCH0
-Res0	13:12
-Field	11	HAFT
-Field	10	PTTWI
-Res0	9:6
-Field	5	D128
-Field	4	AIE
-Field	3	POE
-Field	2	E0POE
-Field	1	PIE
-Field	0	PnCH
-EndSysreg
-
-Sysreg	TCR2_EL12	3	5	2	0	3
-Mapping	TCR2_EL1
-EndSysreg
-
-Sysreg	TCR2_EL2	3	4	2	0	3
-Res0	63:16
-Field	15	DisCH1
-Field	14	DisCH0
-Field	13	AMEC1
-Field	12	AMEC0
-Field	11	HAFT
-Field	10	PTTWI
-Res0	9:6
-Field	5	D128
-Field	4	AIE
-Field	3	POE
-Field	2	E0POE
-Field	1	PIE
-Field	0	PnCH
-EndSysreg
-
-SysregFields MAIR2_ELx
-Field	63:56	Attr7
-Field	55:48	Attr6
-Field	47:40	Attr5
-Field	39:32	Attr4
-Field	31:24	Attr3
-Field	23:16	Attr2
-Field	15:8	Attr1
-Field	7:0	Attr0
-EndSysregFields
-
-Sysreg	MAIR2_EL1	3	0	10	2	1
-Fields	MAIR2_ELx
-EndSysreg
-
-Sysreg	MAIR2_EL2	3	4	10	1	1
-Fields	MAIR2_ELx
-EndSysreg
-
-Sysreg	AMAIR2_EL1	3	0	10	3	1
-Field	63:0	ImpDef
-EndSysreg
-
-Sysreg	AMAIR2_EL2	3	4	10	3	1
-Field	63:0	ImpDef
-EndSysreg
-
-SysregFields PIRx_ELx
-Field	63:60	Perm15
-Field	59:56	Perm14
-Field	55:52	Perm13
-Field	51:48	Perm12
-Field	47:44	Perm11
-Field	43:40	Perm10
-Field	39:36	Perm9
-Field	35:32	Perm8
-Field	31:28	Perm7
-Field	27:24	Perm6
-Field	23:20	Perm5
-Field	19:16	Perm4
-Field	15:12	Perm3
-Field	11:8	Perm2
-Field	7:4	Perm1
-Field	3:0	Perm0
-EndSysregFields
-
-Sysreg	PIRE0_EL1	3	0	10	2	2
-Fields	PIRx_ELx
-EndSysreg
-
 Sysreg	PIRE0_EL12	3	5	10	2	2
 Mapping	PIRE0_EL1
 EndSysreg
 
-Sysreg	PIRE0_EL2	3	4	10	2	2
-Fields	PIRx_ELx
-EndSysreg
-
-Sysreg	PIR_EL1		3	0	10	2	3
-Fields	PIRx_ELx
-EndSysreg
-
 Sysreg	PIR_EL12	3	5	10	2	3
 Mapping	PIR_EL1
 EndSysreg
 
-Sysreg	PIR_EL2		3	4	10	2	3
-Fields	PIRx_ELx
-EndSysreg
-
-Sysreg	POR_EL0		3	3	10	2	4
-Fields	PIRx_ELx
-EndSysreg
-
-Sysreg	POR_EL1		3	0	10	2	4
-Fields	PIRx_ELx
-EndSysreg
-
-Sysreg	POR_EL2		3	4	10	2	4
-Fields	PIRx_ELx
-EndSysreg
-
 Sysreg	POR_EL12	3	5	10	2	4
 Mapping	POR_EL1
 EndSysreg
 
-Sysreg	S2POR_EL1	3	0	10	2	5
-Fields	PIRx_ELx
-EndSysreg
-
-Sysreg	S2PIR_EL2	3	4	10	2	5
-Fields	PIRx_ELx
-EndSysreg
-
-Sysreg	LORSA_EL1	3	0	10	4	0
-Res0	63:52
-Field	51:16	SA
-Res0	15:1
-Field	0	Valid
-EndSysreg
-
-Sysreg	LOREA_EL1	3	0	10	4	1
-Res0	63:52
-Field	51:48	EA_51_48
-Field	47:16	EA_47_16
-Res0	15:0
-EndSysreg
-
-Sysreg	LORN_EL1	3	0	10	4	2
-Res0	63:8
-Field	7:0	Num
-EndSysreg
-
-Sysreg	LORC_EL1	3	0	10	4	3
-Res0	63:10
-Field	9:2	DS
-Res0	1
-Field	0	EN
-EndSysreg
-
-Sysreg	MPAMIDR_EL1	3	0	10	4	4
-Res0	63:62
-Field	61	HAS_SDEFLT
-Field	60	HAS_FORCE_NS
-Field	59	SP4
-Field	58	HAS_TIDR
-Field	57	HAS_ALTSP
-Res0	56:40
-Field	39:32	PMG_MAX
-Res0	31:21
-Field	20:18	VPMR_MAX
-Field	17	HAS_HCR
-Res0	16
-Field	15:0	PARTID_MAX
-EndSysreg
-
-Sysreg	LORID_EL1	3	0	10	4	7
-Res0	63:24
-Field	23:16	LD
-Res0	15:8
-Field	7:0	LR
-EndSysreg
-
-Sysreg	MPAM1_EL1	3	0	10	5	0
-Field	63	MPAMEN
-Res0	62:61
-Field	60 FORCED_NS
-Res0	59:55
-Field	54	ALTSP_FRCD
-Res0	53:48
-Field	47:40	PMG_D
-Field	39:32	PMG_I
-Field	31:16	PARTID_D
-Field	15:0	PARTID_I
-EndSysreg
-
-Sysreg	MPAM0_EL1	3	0	10	5	1
-Res0	63:48
-Field	47:40	PMG_D
-Field	39:32	PMG_I
-Field	31:16	PARTID_D
-Field	15:0	PARTID_I
-EndSysreg
-
-Sysreg	ISR_EL1	3	0	12	1	0
-Res0	63:11
-Field	10	IS
-Field	9	FS
-Field	8	A
-Field	7	I
-Field	6	F
-Res0	5:0
-EndSysreg
-
-Sysreg	ICC_NMIAR1_EL1	3	0	12	9	5
-Res0	63:24
-Field	23:0	INTID
-EndSysreg
-
-Sysreg	TRBLIMITR_EL1	3	0	9	11	0
-Field	63:12	LIMIT
-Res0	11:7
-Field	6	XE
-Field	5	nVM
-Enum	4:3	TM
-	0b00	STOP
-	0b01	IRQ
-	0b11	IGNR
-EndEnum
-Enum	2:1	FM
-	0b00	FILL
-	0b01	WRAP
-	0b11	CBUF
-EndEnum
-Field	0	E
-EndSysreg
-
-Sysreg	TRBPTR_EL1	3	0	9	11	1
-Field	63:0	PTR
-EndSysreg
-
-Sysreg	TRBBASER_EL1	3	0	9	11	2
-Field	63:12	BASE
-Res0	11:0
-EndSysreg
-
-Sysreg	TRBSR_EL1	3	0	9	11	3
-Res0	63:56
-Field	55:32	MSS2
-Field	31:26	EC
-Res0	25:24
-Field	23	DAT
-Field	22	IRQ
-Field	21	TRG
-Field	20	WRAP
-Res0	19
-Field	18	EA
-Field	17	S
-Res0	16
-Field	15:0	MSS
-EndSysreg
-
-Sysreg	TRBMAR_EL1	3	0	9	11	4
-Res0	63:12
-Enum	11:10	PAS
-	0b00	SECURE
-	0b01	NON_SECURE
-	0b10	ROOT
-	0b11	REALM
-EndEnum
-Enum	9:8	SH
-	0b00	NON_SHAREABLE
-	0b10	OUTER_SHAREABLE
-	0b11	INNER_SHAREABLE
-EndEnum
-Field	7:0	Attr
-EndSysreg
-
-Sysreg	TRBTRG_EL1	3	0	9	11	6
-Res0	63:32
-Field	31:0	TRG
+Sysreg	MPAM1_EL12	3	5	10	5	0
+Fields	MPAM1_ELx
 EndSysreg
 
-Sysreg	TRBIDR_EL1	3	0	9	11	7
-Res0	63:12
-Enum	11:8	EA
-	0b0000	NON_DESC
-	0b0001	IGNORE
-	0b0010	SERROR
-EndEnum
-Res0	7:6
-Field	5	F
-Field	4	P
-Field	3:0	Align
+Sysreg	CONTEXTIDR_EL12	3	5	13	0	1
+Mapping	CONTEXTIDR_EL1
 EndSysreg
-- 
2.34.1

[PATCH 5/5] arm64/sysreg: Enforce sorting

[James Clark]

Make an unsorted sysreg file a build error so it stays sorted.

Signed-off-by: James Clark <james.clark@linaro.org>
---
 arch/arm64/tools/gen-sysreg.awk | 7 +++++++
 1 file changed, 7 insertions(+)

diff --git a/arch/arm64/tools/gen-sysreg.awk b/arch/arm64/tools/gen-sysreg.awk
index 7f578216dc68..00a8391f373d 100755
--- a/arch/arm64/tools/gen-sysreg.awk
+++ b/arch/arm64/tools/gen-sysreg.awk
@@ -98,6 +98,7 @@ BEGIN {
 
 	__current_block_depth = 0
 	__current_block[__current_block_depth] = "Root"
+	__last_sysreg_sort_val = 0
 }
 
 END {
@@ -156,6 +157,12 @@ $1 == "Sysreg" && block_current() == "Root" {
 	crm = $6
 	op2 = $7
 
+	sort_val = sprintf("%02d", $3) sprintf("%02d", $4) sprintf("%02d", $5) \
+			sprintf("%02d", $6) sprintf("%02d", $7)
+	if (sort_val < __last_sysreg_sort_val)
+		fatal($2 ": Sysregs should be sorted by encoding")
+	__last_sysreg_sort_val = sort_val
+
 	res0 = "UL(0)"
 	res1 = "UL(0)"
 	unkn = "UL(0)"
-- 
2.34.1

Re: [PATCH 5/5] arm64/sysreg: Enforce sorting

[Mark Brown]

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On Wed, Jan 15, 2025 at 01:42:57PM +0000, James Clark wrote:
> Make an unsorted sysreg file a build error so it stays sorted.

Reviewed-by: Mark Brown <broonie@kernel.org>

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