From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id D714BC46CA1 for ; Mon, 18 Sep 2023 09:46:21 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234941AbjIRJpt (ORCPT ); Mon, 18 Sep 2023 05:45:49 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:52328 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240912AbjIRJp3 (ORCPT ); Mon, 18 Sep 2023 05:45:29 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 057D4CC4 for ; Mon, 18 Sep 2023 02:44:14 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 6F0EDC433C7; Mon, 18 Sep 2023 09:44:14 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695030254; bh=d5QNa0rFPQKJhTfE6aV8V13ZKrAJ2zdet4hfSfVVYpg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=k15vNTBJeQ2IwRF75jvpvYHPug/r/abpjSo7sVgKfzVncJt7UNob0Yz70j3Vqva6F iSY7X4waG67B2Pur4aFcXrlfwJCeapbh8K9o60uP7Z1gSszBvar3+u1Mj6sxN8JFMd ICTCnrD0gs6Bhq810dGQ4k7Lq5FrK7M3TA2LBvBfH2U+IFQjfBcifecmPZQvabc033 uq6EtC4WhGmdvKcwGreiNljuJUr97bsqKDq10k52FBQG46IbZILoU8evAKK10tS4rW LvoTiQ7z8AbJKyyJ70PUw+3Y0OG3xNfThziyNA7PWFlQLHvxbVOCHZY4lUFY9GqeMU RLMfPqaMFmyrA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qiAnb-00DuQH-Us; Mon, 18 Sep 2023 10:44:12 +0100 Date: Mon, 18 Sep 2023 10:44:11 +0100 Message-ID: <867conerys.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH 3/3] KVM: arm64: nv: Handle all _EL02 and _EL12 registers In-Reply-To: <20230913185209.32282-4-miguel.luis@oracle.com> References: <20230913185209.32282-1-miguel.luis@oracle.com> <20230913185209.32282-4-miguel.luis@oracle.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 13 Sep 2023 19:52:08 +0100, Miguel Luis wrote: > > Specify both _EL02 and _EL12 system registers. > > Signed-off-by: Miguel Luis > --- > arch/arm64/kvm/emulate-nested.c | 35 +++++++++++++++++++++++++++++---- > 1 file changed, 31 insertions(+), 4 deletions(-) > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 9aa1c06abdb7..957afd97e488 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -690,10 +690,37 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { > SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3), > sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV), > /* All _EL02, _EL12 registers */ > - SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), > - sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), > - SR_RANGE_TRAP(sys_reg(3, 5, 12, 0, 0), > - sys_reg(3, 5, 14, 15, 7), CGT_HCR_NV), > + SR_TRAP(SYS_SCTLR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_CPACR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_SCTLR2_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_ZCR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_TRFCR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_SMCR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_TTBR0_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_TTBR1_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_TCR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_TCR2_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_SPSR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_ELR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_AFSR0_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_AFSR1_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_ESR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_TFSR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_FAR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_BRBCR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_PMSCR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_MAIR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_AMAIR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_VBAR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_CONTEXTIDR_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_SCXTNUM_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_CNTKCTL_EL12, CGT_HCR_NV), > + SR_TRAP(SYS_CNTP_TVAL_EL02, CGT_HCR_NV), > + SR_TRAP(SYS_CNTP_CTL_EL02, CGT_HCR_NV), > + SR_TRAP(SYS_CNTP_CVAL_EL02, CGT_HCR_NV), > + SR_TRAP(SYS_CNTV_TVAL_EL02, CGT_HCR_NV), > + SR_TRAP(SYS_CNTV_CTL_EL02, CGT_HCR_NV), > + SR_TRAP(SYS_CNTV_CVAL_EL02, CGT_HCR_NV), > SR_TRAP(OP_AT_S1E2R, CGT_HCR_NV), > SR_TRAP(OP_AT_S1E2W, CGT_HCR_NV), > SR_TRAP(OP_AT_S12E1R, CGT_HCR_NV), While I could see the problem with the EL2 registers, I'm not convinced by this patch. Is there an actual case for non _EL02, non _EL12 registers that are included in the two ranges above? Thanks, M. -- Without deviation from the norm, progress is not possible.