From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id C36442DE6E8 for ; Thu, 3 Jul 2025 08:44:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751532245; cv=none; b=mW3zaUYEr4ZTzG9QqeB7Fvz8Dv2bQQVL2q8sBdkm6MbqnfjcMBfsTgp+6vIN8Ynvn4Z+sEVoXvgqlhOrCZ5iIYABm+28n6siTJo3SoqoLxGjnFGtt+wXObtny3FpQKCEqQF/YJKOvx9/JO/j4JiichQyunYlFlBeXBgnBUomVGg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1751532245; c=relaxed/simple; bh=HBMzhFOttPyIWUwK5cb5WZMKbe36+j/NTDCw+TRnB3c=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=oYgUM06Z6BCXjlxtUrNiVbqi8qx+QajvyIJpDSCmWShalEdVaTjGVWt4mEEkKV47pJg4FNwVwLvFi3aUcf5Y4Cpwz8JKnWsYtzBuQ/RALBXahWoG3N+OzwnkWM1tbYclZcOeYIa/Xtiq2l+jtxV6ohxJN4YF/+N1zCJFY/zeveM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=P7jt3Fpb; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="P7jt3Fpb" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 44CB7C4CEE3; Thu, 3 Jul 2025 08:44:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1751532245; bh=HBMzhFOttPyIWUwK5cb5WZMKbe36+j/NTDCw+TRnB3c=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=P7jt3Fpb4wT5/Ob9nkRVrO45tKz0jWfnJOaEahdnMTl/gUvA2wJFpE6rX20H+gKQo chkCO+aA+/TjK/FhADXsIEZABdcr9JaDQXRyR8fn8SiqwwqInSzfS3dgQWUf7lRqQz 2WTzPSePO7112PMCguiTBca5SObSUIn51Dzjr4QSBzRBxAdeAjWyrw/Eifn7iJ1Y+V nKK78rDq8IY7ukgxfwrjyZ9nzsAX5AIrXuZ1q/8KN6gFxYfZ6qsDQVnSecTh4obtWj cE6Cw5zVQM7kmP/B5pvhpUeRG5VFqhm3RzdRAdLPjTqDq6JoAQ9yoV0wNX37Bz9/XE 0V9+iXChLACJw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uXFY3-00CEFo-0H; Thu, 03 Jul 2025 09:44:03 +0100 Date: Thu, 03 Jul 2025 09:44:02 +0100 Message-ID: <868ql5br59.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Ryan Roberts , Mark Rutland , linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64/mm: Drop wrong writes into TCR2_EL1 In-Reply-To: <20250703050453.136871-1-anshuman.khandual@arm.com> References: <20250703050453.136871-1-anshuman.khandual@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, ryan.roberts@arm.com, mark.rutland@arm.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 03 Jul 2025 06:04:53 +0100, Anshuman Khandual wrote: > > Register X0 contains PIE_E1_ASM and should not be written into REG_TCR2_EL1 > which could have an adverse impact otherwise. This has remained undetected > till now probably because current value for PIE_E1_ASM (0xcc880e0ac0800000) > clears TCR2_EL1 which again gets set subsequently with 'tcr' after checking > for FEAT_TCRX. > > Drop this unwarranted 'msr' which is a stray change from an earlier commit. Looks like I re-introduced this when rebasing on top of 926b66e2ebc8c ("arm64: setup: name 'tcr2' register"), which did remove this line. Might be worth capturing in the commit message. > > Cc: Catalin Marinas > Cc: Will Deacon > Cc: Ryan Roberts > Cc: Marc Zyngier > Cc: Mark Rutland > Cc: linux-arm-kernel@lists.infradead.org > Cc: linux-kernel@vger.kernel.org > Fixes: 7052e808c446 ("arm64/sysreg: Get rid of the TCR2_EL1x SysregFields") > Signed-off-by: Anshuman Khandual > --- > This patch applies on v6.16-rc4 and tested with and without FEAT_S1PIE > enabled. > > arch/arm64/mm/proc.S | 1 - > 1 file changed, 1 deletion(-) > > diff --git a/arch/arm64/mm/proc.S b/arch/arm64/mm/proc.S > index 80d470aa469d..54dccfd6aa11 100644 > --- a/arch/arm64/mm/proc.S > +++ b/arch/arm64/mm/proc.S > @@ -518,7 +518,6 @@ alternative_else_nop_endif > msr REG_PIR_EL1, x0 > > orr tcr2, tcr2, TCR2_EL1_PIE > - msr REG_TCR2_EL1, x0 > > .Lskip_indirection: > Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.