From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 44D1BC46CA1 for ; Mon, 18 Sep 2023 09:43:04 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S240965AbjIRJmk (ORCPT ); Mon, 18 Sep 2023 05:42:40 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56772 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S240881AbjIRJmH (ORCPT ); Mon, 18 Sep 2023 05:42:07 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 5F5A3E52 for ; Mon, 18 Sep 2023 02:40:21 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id EA1D5C433C8; Mon, 18 Sep 2023 09:40:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1695030021; bh=HVSpFQnmXQ6FFjFm3ben4gsTYRSP8yFtpc7kR540pqk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=m01BeqeWOZUF7RuUbLKaq2WW41I4cDu3hC2ZRxHGt7JnErfhOxBgQiuFloTVFr250 ftjLpTaMf8jMLQ+b0L/XloOps2FYp4+soBM+2TjgAwbQzhHs9RLmh0kslkPoAkFL6p /mtGNe43CnsROOyJfVxp0lw50t/TXXZ2XvmWLaAoUXwgRtQOdW2YpQXovCg3sbDInv Mfm8XhNovFVuxB2VmaQiSmnvihnNfLXkx5d+GqDTXFyf82QLt5GGNyx/17ZhmetJLv HBIcdwgnf/ShQS38U5xhN0CO6tV4PRfZPi3P6qcYRdOaOtkG3+8Pe69k3zV7EINApL X26nE++7OIAlA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qiAjq-00DuMf-CM; Mon, 18 Sep 2023 10:40:18 +0100 Date: Mon, 18 Sep 2023 10:40:17 +0100 Message-ID: <868r93es5a.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH 2/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization In-Reply-To: <20230913185209.32282-3-miguel.luis@oracle.com> References: <20230913185209.32282-1-miguel.luis@oracle.com> <20230913185209.32282-3-miguel.luis@oracle.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org Hi Miguel, On Wed, 13 Sep 2023 19:52:07 +0100, Miguel Luis wrote: > > Some _EL1 registers got included in the _EL2 ranges, which are not > affected by NV. Remove them and fine grain the ranges to exclusively > include the _EL2 ones. > > Signed-off-by: Miguel Luis > --- > arch/arm64/kvm/emulate-nested.c | 44 ++++++++++++++++++++++++++++----- > 1 file changed, 38 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 9ced1bf0c2b7..9aa1c06abdb7 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -649,14 +649,46 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { > SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), > /* All _EL2 registers */ > SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0), > - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV), > + sys_reg(3, 4, 4, 0, 1), CGT_HCR_NV), It would be good if the commit message explained that you are folding SPSR/ELR into the existing range. Also, please keep the two ends of the ranges vertically aligned. > /* Skip the SP_EL1 encoding... */ > - SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), > - SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), > - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1), > - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV), > + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0), > + sys_reg(3, 4, 10, 6, 7), CGT_HCR_NV), > + /* skip MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, > + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, > + * VMECID_P_EL2. > + */ Please follow the kernel comment format. Also, why are you skipping the MEC registers, but not the MPAM ones? At least indicate a rationale for this. > SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0), > - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV), > + sys_reg(3, 4, 12, 1, 1), CGT_HCR_NV), > + /* ICH_AP0R_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, > + SYS_ICH_AP0R3_EL2, CGT_HCR_NV), > + /* ICH_AP1R_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, > + SYS_ICH_AP1R3_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(sys_reg(3, 4, 12, 9, 5), > + sys_reg(3, 4, 12, 11, 7), CGT_HCR_NV), > + /* ICH_LR_EL2 */ > + SR_TRAP(SYS_ICH_LR0_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR1_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR2_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR3_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR4_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR5_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR6_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR7_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR8_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR9_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR10_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR11_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR12_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR13_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR14_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_LR15_EL2, CGT_HCR_NV), You could describe all the LRs a single range. > + SR_RANGE_TRAP(sys_reg(3, 4, 13, 0, 1), > + sys_reg(3, 4, 13, 0, 7), CGT_HCR_NV), > + /* skip AMEVCNTVOFF0_EL2 and AMEVCNTVOFF1_EL2 */ Why? > + SR_RANGE_TRAP(sys_reg(3, 4, 14, 0, 3), > + sys_reg(3, 4, 14, 5, 2), CGT_HCR_NV), > /* All _EL02, _EL12 registers */ > SR_RANGE_TRAP(sys_reg(3, 5, 0, 0, 0), > sys_reg(3, 5, 10, 15, 7), CGT_HCR_NV), Thanks, M. -- Without deviation from the norm, progress is not possible.