From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 060551EB1AA; Thu, 28 Aug 2025 14:05:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389923; cv=none; b=SzQhq6gOK22MHHrrNsVsUuZw9XIyNb3yGlPbQe3oGw9hVQUeTjdEnvh1fGd/Vl5C3tgw4+21Vgcobq/Hz6Kcye9u/7qvdquPFT++T97bcQxZenjeFMKbDb6NDlX4+2l3ZHIRACqGuuOb8hdxIK5tQIQ+qpBqJ0LW3/6qiFtCXmw= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1756389923; c=relaxed/simple; bh=DyNh/B5mAGR7TnY7MatHO1yPHUOMMK2nagZ3lUWn2fA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=WKTyJZBxfbd6HcULd0/bK2CvtCrzek8J567EXKK1VsXNUkLr9t8KZQY9E703E9mTdeCRj2NKWeMrWIUcBhcoSF3LRYsX+cs0/oV+p48sb3r5utR8CpKhABzrneBN/fQUEKOBA6urG/PJ+jae1OGCmumC44s3Jvr/6e4eApN1atY= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=H+zo2fE6; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="H+zo2fE6" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 85578C4CEEB; Thu, 28 Aug 2025 14:05:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1756389922; bh=DyNh/B5mAGR7TnY7MatHO1yPHUOMMK2nagZ3lUWn2fA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=H+zo2fE6t4kb7opwDirCTmZXQYUMxdvDUzaEKmgm8oXo5Y/8fdTsykOW8ssM5iF+D SmedYJyt043ervcAhMuYbe8ar+hbn7oFmJsq22z8U6+H2RIfzztrWWqTszG4rGAhwd yzBFfas+iTFaYelbOfN0IK7GUHRM8SskLDVX6yP8Job6MSKqD5TiFWdb6F2XxO3efU cBZ73/1djxNknr85AEIcZHyRIBxY1ujZEKIWxq8qWu4rl4nsKhy0ixUBGdKbbAefws T1nGT5HPB82ySUXmGtOvqLzYWC/DG4BL/X1u7pWZyB9bqMLmWOoBvJA9LmUNcviwzi 2fII+8TyG8u0A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1urdFf-00000001H7W-31tP; Thu, 28 Aug 2025 14:05:19 +0000 Date: Thu, 28 Aug 2025 15:05:19 +0100 Message-ID: <86a53jee3k.wl-maz@kernel.org> From: Marc Zyngier To: Sascha Bischoff Cc: "linux-arm-kernel@lists.infradead.org" , "kvmarm@lists.linux.dev" , "linux-kernel@vger.kernel.org" , "kvm@vger.kernel.org" , nd , "oliver.upton@linux.dev" , Joey Gouly , Suzuki Poulose , "yuzenghui@huawei.com" , "will@kernel.org" , "tglx@linutronix.de" , "lpieralisi@kernel.org" , Timothy Hayes Subject: Re: [PATCH 1/5] KVM: arm64: Allow ICC_SRE_EL2 accesses on a GICv5 host In-Reply-To: <20250828105925.3865158-2-sascha.bischoff@arm.com> References: <20250828105925.3865158-1-sascha.bischoff@arm.com> <20250828105925.3865158-2-sascha.bischoff@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: Sascha.Bischoff@arm.com, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org, kvm@vger.kernel.org, nd@arm.com, oliver.upton@linux.dev, Joey.Gouly@arm.com, Suzuki.Poulose@arm.com, yuzenghui@huawei.com, will@kernel.org, tglx@linutronix.de, lpieralisi@kernel.org, Timothy.Hayes@arm.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 28 Aug 2025 11:59:42 +0100, Sascha Bischoff wrote: > > The bet0 release of the GICv5 specification didn't include the > ICC_SRE_EL2 register as part of FEAT_GCIE_LEGACY. This was an > oversight, and support for this register has been added as of the bet1 > release of the specification. > > Remove the guarding in the vGICv3 code that skipped the ICC_SRE_EL2 > accesses for a GICv5 host. As a result of this change, it now becomes > possible to use nested virtualisation on a GICv5 host when running > legacy GICv3-based VMs. > > Signed-off-by: Sascha Bischoff > --- > arch/arm64/kvm/hyp/vgic-v3-sr.c | 27 +++++++-------------------- > 1 file changed, 7 insertions(+), 20 deletions(-) > > diff --git a/arch/arm64/kvm/hyp/vgic-v3-sr.c b/arch/arm64/kvm/hyp/vgic-v3-sr.c > index d81275790e69..7dbfd35a63a8 100644 > --- a/arch/arm64/kvm/hyp/vgic-v3-sr.c > +++ b/arch/arm64/kvm/hyp/vgic-v3-sr.c > @@ -296,19 +296,12 @@ void __vgic_v3_activate_traps(struct vgic_v3_cpu_if *cpu_if) > } > > /* > - * GICv5 BET0 FEAT_GCIE_LEGACY doesn't include ICC_SRE_EL2. This is due > - * to be relaxed in a future spec release, at which point this in > - * condition can be dropped. > + * Prevent the guest from touching the ICC_SRE_EL1 system > + * register. Note that this may not have any effect, as > + * ICC_SRE_EL2.Enable being RAO/WI is a valid implementation. > */ > - if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) { > - /* > - * Prevent the guest from touching the ICC_SRE_EL1 system > - * register. Note that this may not have any effect, as > - * ICC_SRE_EL2.Enable being RAO/WI is a valid implementation. > - */ > - write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, > - ICC_SRE_EL2); > - } > + write_gicreg(read_gicreg(ICC_SRE_EL2) & ~ICC_SRE_EL2_ENABLE, > + ICC_SRE_EL2); At some point, it would be great to elide this on systems where GICv2-on-v3 doesn't exist, as there is no way for the guest to disable the system register view. This would avoid a couple of pointless traps on each entry-exit for a nested guest. > > /* > * If we need to trap system registers, we must write > @@ -329,14 +322,8 @@ void __vgic_v3_deactivate_traps(struct vgic_v3_cpu_if *cpu_if) > cpu_if->vgic_vmcr = read_gicreg(ICH_VMCR_EL2); > } > > - /* > - * Can be dropped in the future when GICv5 spec is relaxed. See comment > - * above. > - */ > - if (!cpus_have_final_cap(ARM64_HAS_GICV5_CPUIF)) { > - val = read_gicreg(ICC_SRE_EL2); > - write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); > - } > + val = read_gicreg(ICC_SRE_EL2); > + write_gicreg(val | ICC_SRE_EL2_ENABLE, ICC_SRE_EL2); Same here. That's two back-to-back traps for values that cannot realistically change on non-v2-compat systems (i.e. relatively modern machines). No need to respin for that, but I may end-up posting a follow-up to clean this up. Thanks, M. -- Without deviation from the norm, progress is not possible.