From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CB11C25B48 for ; Thu, 26 Oct 2023 10:06:47 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229823AbjJZKGr (ORCPT ); Thu, 26 Oct 2023 06:06:47 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:42660 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229567AbjJZKGp (ORCPT ); Thu, 26 Oct 2023 06:06:45 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0F16E198 for ; Thu, 26 Oct 2023 03:06:43 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9F8C8C433C8; Thu, 26 Oct 2023 10:06:42 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1698314802; bh=zYxEWHl5RzRUDPE2SYQ5Vl65FzykHZH3gpuF9A0PXVc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=GJA7F8Ndv/JVhi1z+gSbh17fng8BueSN/HoUvsQR/K3etpaFM+OhVndNEgFt1uY/n hGVH7faXPQ3dmiENKOR8z9GvbYv+VYGzXqzgyUqF8wrbKzAp+9I28T5SE57YAYzogI 64o5ZmEmxPoYmPHCvBw6fwChvMW87MLW15X/stN9LF45yNcLRbRCuNiiwalWQGy17G wm0ISB3emPz4X3dFuUT5udUwO7RiPFSO7hOAqHClQhmmMtzS5E4ibS7rior+5Ruymk lxGnM1HAuX76m+mj3olCPppmuBCh58iLZnNlnh6/4w7ylK7z5sBfedxV85To/2b7D4 0pWJsx/GwPKaA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qvxGC-007qyR-4p; Thu, 26 Oct 2023 11:06:40 +0100 Date: Thu, 26 Oct 2023 11:06:38 +0100 Message-ID: <86a5s54s0h.wl-maz@kernel.org> From: Marc Zyngier To: Ilkka Koskinen Cc: Catalin Marinas , Will Deacon , Zaid Al-Bassam , Geert Uytterhoeven , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: perf: Don't disgard upper 32 bits from PMCEID0/1 registers In-Reply-To: <20231025200815.104017-1-ilkka@os.amperecomputing.com> References: <20231025200815.104017-1-ilkka@os.amperecomputing.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ilkka@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, zalbassam@google.com, geert+renesas@glider.be, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 25 Oct 2023 21:08:15 +0100, Ilkka Koskinen wrote: > > The upper 32 bits of PMCEID[n] registers are used to describe whether > architectural and microarchitectural events in range 0x4000-0x401f > exist. Due to disgarding the bits, the driver made the events invisible, > even if they existed. > > Fixes: df29ddf4f04b ("arm64: perf: Abstract system register accesses away") > Reported-by: Carl Worth > Signed-off-by: Ilkka Koskinen > --- > arch/arm64/include/asm/arm_pmuv3.h | 4 ++-- > 1 file changed, 2 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/include/asm/arm_pmuv3.h b/arch/arm64/include/asm/arm_pmuv3.h > index 18dc2fb3d7b7..3e92b7cb57a4 100644 > --- a/arch/arm64/include/asm/arm_pmuv3.h > +++ b/arch/arm64/include/asm/arm_pmuv3.h > @@ -126,12 +126,12 @@ static inline void write_pmuserenr(u32 val) > write_sysreg(val, pmuserenr_el0); > } > > -static inline u32 read_pmceid0(void) > +static inline u64 read_pmceid0(void) > { > return read_sysreg(pmceid0_el0); > } > > -static inline u32 read_pmceid1(void) > +static inline u64 read_pmceid1(void) > { > return read_sysreg(pmceid1_el0); > } This is necessary, but not sufficient. You also need to update the corresponding 32bit accessors to match this behaviour. Something along the lines of the patch below M. diff --git a/arch/arm/include/asm/arm_pmuv3.h b/arch/arm/include/asm/arm_pmuv3.h index 72529f5e2bed..90841cb7ce43 100644 --- a/arch/arm/include/asm/arm_pmuv3.h +++ b/arch/arm/include/asm/arm_pmuv3.h @@ -23,6 +23,8 @@ #define PMUSERENR __ACCESS_CP15(c9, 0, c14, 0) #define PMINTENSET __ACCESS_CP15(c9, 0, c14, 1) #define PMINTENCLR __ACCESS_CP15(c9, 0, c14, 2) +#define PMCEID2 __ACCESS_CP15(c9, 0, c14, 4) +#define PMCEID3 __ACCESS_CP15(c9, 0, c14, 5) #define PMMIR __ACCESS_CP15(c9, 0, c14, 6) #define PMCCFILTR __ACCESS_CP15(c14, 0, c15, 7) @@ -205,16 +207,6 @@ static inline void write_pmuserenr(u32 val) write_sysreg(val, PMUSERENR); } -static inline u32 read_pmceid0(void) -{ - return read_sysreg(PMCEID0); -} - -static inline u32 read_pmceid1(void) -{ - return read_sysreg(PMCEID1); -} - static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} static inline void kvm_clr_pmu_events(u32 clr) {} static inline bool kvm_pmu_counter_deferred(struct perf_event_attr *attr) @@ -231,6 +223,7 @@ static inline void kvm_vcpu_pmu_resync_el0(void) {} /* PMU Version in DFR Register */ #define ARMV8_PMU_DFR_VER_NI 0 +#define ARMV8_PMU_DFR_VER_V3P1 0x4 #define ARMV8_PMU_DFR_VER_V3P4 0x5 #define ARMV8_PMU_DFR_VER_V3P5 0x6 #define ARMV8_PMU_DFR_VER_IMP_DEF 0xF @@ -251,4 +244,24 @@ static inline bool is_pmuv3p5(int pmuver) return pmuver >= ARMV8_PMU_DFR_VER_V3P5; } +static inline u64 read_pmceid0(void) +{ + u64 val = read_sysreg(PMCEID0); + + if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1) + val |= (u64)read_sysreg(PMCEID2) << 32; + + return val; +} + +static inline u64 read_pmceid1(void) +{ + u64 val = read_sysreg(PMCEID1); + + if (read_pmuver() >= ARMV8_PMU_DFR_VER_V3P1) + val |= (u64)read_sysreg(PMCEID3) << 32; + + return val; +} + #endif -- Without deviation from the norm, progress is not possible.