From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 846C1A55 for ; Thu, 29 May 2025 10:10:53 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748513453; cv=none; b=cUwQxjByRg1C4yM4P/kgoJJBpmpjrMan81oTZtCpOn/SYsG9/zkhmUtoArFc+biP/0lzlQW+cu9xf9ac26jAysiQjWRRSXyRb1YUKm/O4n6VihNLGoEU/TAdo9FcNy5LDkl3ZSzRLBq9Sx1zKK+uV4g0vE8wBMxgmz9GoETcyTQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1748513453; c=relaxed/simple; bh=2SPYYnFsmGwjObQFoYHVAiWE4pV7Oa7ae04lMbI5XuU=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=ezEQFzZrgA4ZHZ1bSLsUooJ2Xg5FEXS2qEkzA8jfGPos2YdBx+h/KipNrd2Vl2XqSOK++9lrDs9EszHhPcFLZ8irWHoin5VNcMgtS5lkshIg2vtc980k4bkd+mH2M5ilLrNikGx0fcfBIe29xRQi9LUc+c57YQ5aGxDBlc9DGbk= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TUcB3wHU; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TUcB3wHU" Received: by smtp.kernel.org (Postfix) with ESMTPSA id EE49EC4CEE7; Thu, 29 May 2025 10:10:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1748513453; bh=2SPYYnFsmGwjObQFoYHVAiWE4pV7Oa7ae04lMbI5XuU=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=TUcB3wHUmCVqLoGVnAoDIV50ON/bLiJCsR/YyoPh8q7CfuBzyFrVehALmhf78uCzV 3MyNyUkspKXSiCzx92+WJZ3JtuPxW9taxrrj7LacpOocaOg+e0REJQXBsEiNYFgRqK MQNXU0tCc7R49U4ijpM+RMpnlYRtvTAbvf6F21UtMBcbHNfsj0ShSXN/15SW3DsNI8 LDPsdcQ8Ox4kuw1UkE64ztiRTl8vgOGyoF80CtAZhkHYMV3h9WP2y7gbdc8oLWiVuc A517vrwk+Q6hDegIBhp7pGWNJw+XhSc+Ox6gzvPUDWHWgnqE/NirNtwMHS8RYNbltR cDfHEOpDsz6Hg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uKaDq-001WiE-HB; Thu, 29 May 2025 11:10:50 +0100 Date: Thu, 29 May 2025 11:10:50 +0100 Message-ID: <86bjrbenh1.wl-maz@kernel.org> From: Marc Zyngier To: Xi Ruoyao Cc: James Morse , Anshuman Khandual , Ben Horgan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Shameer Kolothum , Mingcong Bai , Shaopeng Tan Subject: Re: [PATCH v3] arm64: Add override for MPAM In-Reply-To: <86cybrenvx.wl-maz@kernel.org> References: <20250516102556.9688-1-xry111@xry111.site> <86cybrenvx.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: xry111@xry111.site, james.morse@arm.com, anshuman.khandual@arm.com, ben.horgan@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, shameerali.kolothum.thodi@huawei.com, jeffbai@aosc.io, tan.shaopeng@fujitsu.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 29 May 2025 11:01:54 +0100, Marc Zyngier wrote: > > So you would need to: > > - nuke both MPAM and MPAM_frac in their respective ID registers, > ensuring that we effectively advertise the absence of MPAM > > - either check for both fields wherever we currently refer only to > MPAM, as what we have today looks fragile, or unconditionally > override both ID fields if the HW actually implements MPAMv0.1. > > I personally think the former is easier to implement. > > Note that these would be two separate changes, and that you only need > to implement the first one to achieve what you're after for the > current level of MPAM support. To be completely clear, the change for this patch could be as simple as this: diff --git a/arch/arm64/kernel/pi/idreg-override.c b/arch/arm64/kernel/pi/idreg-override.c index 836e5a9b98d03..bc57b290e5e7b 100644 --- a/arch/arm64/kernel/pi/idreg-override.c +++ b/arch/arm64/kernel/pi/idreg-override.c @@ -155,6 +155,7 @@ static const struct ftr_set_desc pfr1 __prel64_initconst = { FIELD("gcs", ID_AA64PFR1_EL1_GCS_SHIFT, NULL), FIELD("mte", ID_AA64PFR1_EL1_MTE_SHIFT, NULL), FIELD("sme", ID_AA64PFR1_EL1_SME_SHIFT, pfr1_sme_filter), + FIELD("mpam_frac", ID_AA64PFR1_EL1_MPAM_frac_SHIFT, NULL), {} }, }; @@ -247,7 +248,7 @@ static const struct { { "rodata=off", "arm64_sw.rodataoff=1" }, { "arm64.nolva", "id_aa64mmfr2.varange=0" }, { "arm64.no32bit_el0", "id_aa64pfr0.el0=1" }, - { "arm64.nompam", "id_aa64pfr0.mpam=0" }, + { "arm64.nompam", "id_aa64pfr0.mpam=0 id_aa64pfr1.mpam_frac=0" }, }; static int __init parse_hexdigit(const char *p, u64 *v) HTH, M. -- Without deviation from the norm, progress is not possible.