From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A6E291487D5; Wed, 29 Jan 2025 15:33:06 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738164786; cv=none; b=jN60YTITXLujqYQM/1UZ556Per2MctBUAHQIBDgKVYfhMPq5MHKiITp6gTlYTHCvmdn/R4sRChJZh3U+JmCrKfNIay68TLtnxO3tmWm/yizhDWqTz6+vFDuRdbVAz1JoIZPiKX25tt9KrLgjWKvBGfMTMq5BEwnsTn7khRqtX0I= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738164786; c=relaxed/simple; bh=3uM7U4qAvpldPCOBxKRU1v43qglokdN9MY8icFjja2I=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=DCCUP5AJxoWleTXnNgTmbN/tCWA4luFpLBWvbz/cLdTeu23lSmZO39TdCjZQe4uPASp8XvaUlE+I8I7U6smM1LQVODSiAGeIirEjoNh70mUZUBo5xbo9LixyCoC1fPrs1BMhEXH+U+OYiUE9XRSY6F9BLtUvU8zMGqOVXoZwsEE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=GHsKqjCH; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="GHsKqjCH" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 26953C4CED1; Wed, 29 Jan 2025 15:33:06 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738164786; bh=3uM7U4qAvpldPCOBxKRU1v43qglokdN9MY8icFjja2I=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=GHsKqjCH8IcLZNdtcACkT40J7XtaHcBb4y+e64Mowj5qq+gGepeJ01FRVDMXKRH2W WWoYMNliWJSpEXwx08t5Ah4MQJ1tHzRBlNMHOv2Kw8BuNuQg0XjePbAcoOGfhvjJ3T T8GVvCGXRJKLXjxaavwQlFGIV5XN7xihtxyM44GvEmRocTHU6xAE/YLKxUUGSX42rc YFXI5FVxvzxapuJpg8pc0FlFmLWNzMnmdH+TMqgUAdUBIugFOMKr1pfJY3PsXs7m5x NtbtUkVG+WYQ91FW0upw6+eMEWD6TUR8xQtAHczdZA48cBGGExGuhuE5T+T8DoFDWm 4uhZMJmGCQ63A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tdA3r-00GNF6-Kq; Wed, 29 Jan 2025 15:33:03 +0000 Date: Wed, 29 Jan 2025 15:33:02 +0000 Message-ID: <86bjvpvdn5.wl-maz@kernel.org> From: Marc Zyngier To: Colton Lewis Cc: kvm@vger.kernel.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mark.rutland@arm.com, pbonzini@redhat.com, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org Subject: Re: [RFC PATCH 1/4] perf: arm_pmuv3: Introduce module param to partition the PMU In-Reply-To: References: <87ikpzthjk.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: coltonlewis@google.com, kvm@vger.kernel.org, linux@armlinux.org.uk, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mark.rutland@arm.com, pbonzini@redhat.com, shuah@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev, linux-kselftest@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 28 Jan 2025 22:08:27 +0000, Colton Lewis wrote: > > >> + bitmap_set(cpu_pmu->cntr_mask, 0, pmcr_n); > >> + > >> + if (reserved_guest_counters > 0 && reserved_guest_counters < pmcr_n) { > >> + cpu_pmu->hpmn = reserved_guest_counters; > >> + cpu_pmu->partitioned = true; > > > Isn't this going to completely explode on a kernel running at EL1? > > Trying to access an EL2 register at EL1 can do that. I'll add the > appropriate hypercalls. But what about a guest that would get passed the magic parameter? I think you want to prevent that too. > > > Also, how does it work in an asymmetric configuration where some CPUs > > can satisfy the reservation, and some can't? > > The CPUs that can't read their own value of PMCR.N below what the > attempted reservation is and so do not get partitioned. Nothing changes > for that CPU if it can't meet the reservation. That's not what I meant. The question really is: - do we want the reservation to be the number of counters reserved for the host - or do we want it to be for the guest? On symmetric systems, it doesn't matter. On broken big-little systems, this changes everything (it has a direct impact on userspace's ability to use the counters). I think the design should reflect a decision on the above. M. -- Without deviation from the norm, progress is not possible.