From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 1D7A5C433FE for ; Wed, 30 Nov 2022 16:19:03 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229658AbiK3QTB (ORCPT ); Wed, 30 Nov 2022 11:19:01 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41402 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229449AbiK3QTA (ORCPT ); Wed, 30 Nov 2022 11:19:00 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id CC8682AE07 for ; Wed, 30 Nov 2022 08:18:58 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 67FED61C7B for ; Wed, 30 Nov 2022 16:18:58 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id CF3D3C433C1; Wed, 30 Nov 2022 16:18:56 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1669825137; bh=6finBBhB41rftQpLaBk5vk/KMUvYxNjc4FlI2SQgK4o=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=iIsVl68CpjNQALNiIfuVDhoRoZnkBMZY2gLRT5+yI+bUDBV5tGBYU7MD0JItgEICT byzsKlJGX6jbzbvI9WVlpTwglKvj4V6BJxVOfd/09LC7VEd4c1yew97L2VNagSKHoS XHCczQMqRuM5fZOECJeUESLXdb6MEXUra8B1ZYOm3liQl28Stq0Oiu+eLUlzna0GMJ 7t3QSjuSIMJXuypCCQA2Grr9+mzAb1e4O9avFcGaV6Lv1I23ZPAPAL27qSiJI4xg/k hbGqOCsUGRwJfo35hrIyozyMZ72XA8y/3hYE7y7eKGejdNKOPSfq5y8zDX6rpa8cRz U7XrP6rdd/ktg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p0PnS-009cnr-Hp; Wed, 30 Nov 2022 16:18:54 +0000 Date: Wed, 30 Nov 2022 16:18:54 +0000 Message-ID: <86bkoomn4h.wl-maz@kernel.org> From: Marc Zyngier To: Anup Patel Cc: Palmer Dabbelt , Paul Walmsley , Thomas Gleixner , Daniel Lezcano , Atish Patra , Alistair Francis , Anup Patel , linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v13 4/7] RISC-V: Treat IPIs as normal Linux IRQs In-Reply-To: <20221129142449.886518-5-apatel@ventanamicro.com> References: <20221129142449.886518-1-apatel@ventanamicro.com> <20221129142449.886518-5-apatel@ventanamicro.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: apatel@ventanamicro.com, palmer@dabbelt.com, paul.walmsley@sifive.com, tglx@linutronix.de, daniel.lezcano@linaro.org, atishp@atishpatra.org, Alistair.Francis@wdc.com, anup@brainfault.org, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 29 Nov 2022 14:24:46 +0000, Anup Patel wrote: > > Currently, the RISC-V kernel provides arch specific hooks (i.e. > struct riscv_ipi_ops) to register IPI handling methods. The stats > gathering of IPIs is also arch specific in the RISC-V kernel. > > Other architectures (such as ARM, ARM64, and MIPS) have moved away > from custom arch specific IPI handling methods. Currently, these > architectures have Linux irqchip drivers providing a range of Linux > IRQ numbers to be used as IPIs and IPI triggering is done using > generic IPI APIs. This approach allows architectures to treat IPIs > as normal Linux IRQs and IPI stats gathering is done by the generic > Linux IRQ subsystem. > > We extend the RISC-V IPI handling as-per above approach so that arch > specific IPI handling methods (struct riscv_ipi_ops) can be removed > and the IPI handling is done through the Linux IRQ subsystem. > > Signed-off-by: Anup Patel > --- > arch/riscv/Kconfig | 2 + > arch/riscv/include/asm/sbi.h | 10 +- > arch/riscv/include/asm/smp.h | 35 ++++--- > arch/riscv/kernel/Makefile | 1 + > arch/riscv/kernel/cpu-hotplug.c | 3 +- > arch/riscv/kernel/irq.c | 3 +- > arch/riscv/kernel/sbi-ipi.c | 81 ++++++++++++++++ > arch/riscv/kernel/sbi.c | 106 +++----------------- > arch/riscv/kernel/smp.c | 155 +++++++++++++++--------------- > arch/riscv/kernel/smpboot.c | 5 +- > drivers/clocksource/timer-clint.c | 65 ++++++++++--- > drivers/irqchip/Kconfig | 1 + > drivers/irqchip/irq-riscv-intc.c | 55 +++++------ > 13 files changed, 287 insertions(+), 235 deletions(-) > create mode 100644 arch/riscv/kernel/sbi-ipi.c > [...] > diff --git a/arch/riscv/kernel/sbi-ipi.c b/arch/riscv/kernel/sbi-ipi.c > new file mode 100644 > index 000000000000..6466706b03a7 > --- /dev/null > +++ b/arch/riscv/kernel/sbi-ipi.c > @@ -0,0 +1,81 @@ > +// SPDX-License-Identifier: GPL-2.0-only > +/* > + * Multiplex several IPIs over a single HW IPI. > + * > + * Copyright (c) 2022 Ventana Micro Systems Inc. > + */ > + > +#define pr_fmt(fmt) "riscv: " fmt > +#include > +#include > +#include > +#include > +#include > +#include > + > +static int sbi_ipi_virq; > +static DEFINE_PER_CPU_READ_MOSTLY(int, sbi_ipi_dummy_dev); > + > +static irqreturn_t sbi_ipi_handle(int irq, void *dev_id) > +{ > + csr_clear(CSR_IP, IE_SIE); > + ipi_mux_process(); > + return IRQ_HANDLED; Urgh... I really wish I hadn't seen this. This requires a chained handler. You had it before, and yet you dropped it. Why? Either you call ipi_mux_process() from your root interrupt controller, or you implement a chained handler. But not this. Same thing about the clint stuff. M. -- Without deviation from the norm, progress is not possible.