From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 485A2178395 for ; Mon, 21 Oct 2024 17:44:07 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729532648; cv=none; b=XWwy9hYKB48KDhSGtutl4MPoj6oUXKu0cTxy9txkt4SzqRWim8yF7ByOPhDu04xnyqYougu3RuK3T43q/qpmYlCdbO+uSEJ2Td5844NMdUImwN4vtq9RyOBVA/zaC0E0+xRPRKIBsTiPy+ftD2OviY1Eh2izX75rXbSekHZ1kgE= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1729532648; c=relaxed/simple; bh=zGJj8wrBgY1TcEriRxoBtO0t39RL8zcLJTjaqUOxzY8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=NQkvh0gq3E36C5W92sEUvGhfqVNXgkLMdz+IDH/0LnAD0Uq5j1NGdA70uOnLllj6xEVF/HAapKTpO+IbU5FOLJe6ATo1ozK+a5IO2DAqweeJUYYHeca2M5jpKxVuMpfwDF/BAa3dLuY6aLOEVI5wJUKh1eK/oziggJ0iwmfylPc= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=AeKNEo+P; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="AeKNEo+P" Received: by smtp.kernel.org (Postfix) with ESMTPSA id CB781C4CECD; Mon, 21 Oct 2024 17:44:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1729532647; bh=zGJj8wrBgY1TcEriRxoBtO0t39RL8zcLJTjaqUOxzY8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=AeKNEo+PgMPOYrvyzCDrBcnFh+qCvuqpChah5uwy+BlnCB5mTEL13C3xX3gg9YwCp AzUoNRA2PTS9WY5sGKLsaqGQZ4heZ85QS4VJGbfqfgHew20oKzvHLUc2O0AsfHMCgi aBadvkfwgyS3FP4TSQE0GP+DqcUrz4AtZXB3LF3mgqBvh3zM8nV4o58kD9UvhAF64e zPN6L2oOqlBeCLBR0c1G5U52NNn5kRw3SCzZQ6G33OptOX3CEu+VTAfASBNZyHB0Qp O8QFyzdfoIkjEXNhuCnaD7/BlPt/DYe7RDHniNbjwXT1SnMPWyx/PD5O89G8JNC0/S CO34yYSkoTmag== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1t2wRp-005Vkp-HQ; Mon, 21 Oct 2024 18:44:05 +0100 Date: Mon, 21 Oct 2024 18:44:04 +0100 Message-ID: <86cyjt4ahn.wl-maz@kernel.org> From: Marc Zyngier To: Rex Nie Cc: mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, angus.chen@jaguarmicro.com Subject: Re: [PATCH] tools: arm64: add registers read/write tool for arm64 In-Reply-To: <20241021150112.1194-1-rex.nie@jaguarmicro.com> References: <20241021150112.1194-1-rex.nie@jaguarmicro.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: rex.nie@jaguarmicro.com, mcoquelin.stm32@gmail.com, alexandre.torgue@foss.st.com, linux-kernel@vger.kernel.org, linux-stm32@st-md-mailman.stormreply.com, linux-arm-kernel@lists.infradead.org, angus.chen@jaguarmicro.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 21 Oct 2024 16:01:12 +0100, Rex Nie wrote: >=20 > The reg_ctrl kernel module can read/write most aarch64 system registers, > including EL0/1/2/3, which is very useful when hardware debuger (such > as ArmDS5/trace32) is unusable. >=20 > The primary implementation of the reg_ctrl module is as follows: > 1. when the core can directly access the target register, it uses > the MRS/MSR instructions to read/write register. > 2. Otherwise, it performs an SMC call to switch to EL3, where the > register read/write is completed and then return to kernel mode. > I implement an OEM Service in ATF to access register at EL3, > using one SMC function ID for reading and another for writing register= s. >=20 > test steps on my platform with 16x Arm Neoverse N2: > 1. insmod reg_ctrl.ko > 2. cd /sys/kernel/reg_ctrl/system/ > 3. view the directory tree on DUT. > [root@localhost system]# tree > . > =E2=94=9C=E2=94=80=E2=94=80 control > =E2=94=82=C2=A0=C2=A0 =E2=94=94=E2=94=80=E2=94=80 VNCR_EL2 > =E2=94=9C=E2=94=80=E2=94=80 id > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 CCSIDR_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 CLIDR_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 CSSELR_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 CTR_EL0 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 DCZID_EL0 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64AFR0_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64AFR1_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64DFR0_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64DFR1_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64ISAR0_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64ISAR1_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64MMFR0_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64MMFR1_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 ID_AA64PFR0_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=94=E2=94=80=E2=94=80 ID_AA64PFR1_EL1 > =E2=94=9C=E2=94=80=E2=94=80 implementation_defined > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 IMP_CPUACTLR_EL3 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 IMP_CPUECTLR_EL1 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 IMP_CPUPPMCR2_EL3 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 IMP_CPUPPMCR4_EL3 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 IMP_CPUPPMCR5_EL3 > =E2=94=82=C2=A0=C2=A0 =E2=94=9C=E2=94=80=E2=94=80 IMP_CPUPPMCR6_EL3 > =E2=94=82=C2=A0=C2=A0 =E2=94=94=E2=94=80=E2=94=80 IMP_CPUPPMCR_EL3 > =E2=94=94=E2=94=80=E2=94=80 reset > =E2=94=94=E2=94=80=E2=94=80 RMR_EL3 >=20 > 4. read EL1 register on core 0: > [root@localhost system]# taskset -c 0 cat id/ID_AA64PFR0_EL1 > 0x1201111123111112 >=20 > 5. read EL3 register on core 1: > [root@localhost system]# taskset -c 1 cat implementation_defined/IMP_CPUP= PMCR4_EL3 > 0x2000315a10000045 >=20 > 6. set bit 1 of IMP_CPUPPMCR4_EL3 regiter on core 1: > [root@localhost system]# taskset -c 1 echo 0x2000315a10000047 > implement= ation_defined/IMP_CPUPPMCR4_EL3 >=20 > 7. check if bit 1 is set: > [root@localhost system]# taskset -c 1 cat implementation_defined/IMP_CPUP= PMCR4_EL3 > 0x2000315a10000047 >=20 > Signed-off-by: Rex Nie This sort of thing has been NAKed in the past (see [1]), because it is terribly unsafe. I'm afraid the kernel is not a validation tool, and while I understand that this can be useful in extremely narrow cases, it has no place in the upstream kernel. Thanks, M. [1] https://lore.kernel.org/all/20201130174833.41315-1-rongwei.wang@linux.a= libaba.com/ --=20 Without deviation from the norm, progress is not possible.