From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 75D483A963E; Tue, 24 Feb 2026 17:56:01 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771955761; cv=none; b=S7C2msLnwmj2EAcI/gGMB3ZeCDiC1xI66XmlVMyOQN312sqESwP3Gx1tMAr9qRpfSUMBrdzTsLSbx9IhNygoSei0YthItp3nPLXS9FcgY9NYz8gxTP9wzFKPBrNmV0HDV4Z9VsGL+ukX52pvT2sbWUddN0ozLeoxaUddi78Tun4= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1771955761; c=relaxed/simple; bh=QKhb6gfqeqWF4M1NfdEZ6xd9pTG5nQh9Ci3Hs/v4UZg=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=MKQCeKVdLcl1g5iSs8GNXsAwL3HiWJ5ELJYHO3h6PqAwtJJwUp+Ykr4Y4Qn+mu/jRa6/SRHBIO48XIqXQ0FlpPAxKs4Jfyt5T2tOPt0q/X19EM8XwQD/unPpJv2nB7chRDbDc8U8J3m3SjFchqR2bmbYKmtNJcSYyC/WQkB4bKQ= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=KHZmVi3g; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="KHZmVi3g" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 20710C116D0; Tue, 24 Feb 2026 17:56:01 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1771955761; bh=QKhb6gfqeqWF4M1NfdEZ6xd9pTG5nQh9Ci3Hs/v4UZg=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=KHZmVi3g+j4VAdT4fW8Shq4B9qpabNCL6IyfdQW3M9q3DYyPcDY2OeT66plyDPg9k LRy6YI3KMcUbzOPciP6v7zglajAwrxyEvyTnZl5XtZUb72N9rJH8W83joBnRYKo5dh jVSb5mi3xkgiPVgoqkcdq7UtpGjGRZTj8jvxqgxwIXmOJgLETWDUG2cb7agIxTJ5uX /egja3m8Lc5NVeXxhFb4vb3Hd+yV3IFsRJxi9WqLYfnoXdxYGGtzcrsH4Pb60E8L4t e2AjC08WVVZcEWpKWd+VpM7UZ3HXZuIsQp6AXPLdfcoz9oIk7VWYzcffaaYgOeZXfm t6MOtIz6IzppA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vuwda-0000000DRDg-2gJ4; Tue, 24 Feb 2026 17:55:58 +0000 Date: Tue, 24 Feb 2026 17:55:58 +0000 Message-ID: <86ecma9gb5.wl-maz@kernel.org> From: Marc Zyngier To: Sumit Gupta Cc: , , , , , , , , , , , , , , , Subject: Re: [PATCH v2] arm64: topology: Fix false warning in counters_read_on_cpu() for same-CPU reads In-Reply-To: <20260224092714.1242141-1-sumitg@nvidia.com> References: <20260224092714.1242141-1-sumitg@nvidia.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: sumitg@nvidia.com, catalin.marinas@arm.com, will@kernel.org, zhanjie9@hisilicon.com, zhenglifeng1@huawei.com, viresh.kumar@linaro.org, rafael@kernel.org, beata.michalska@arm.com, pierre.gondois@arm.com, ionela.voinescu@arm.com, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, treding@nvidia.com, jonathanh@nvidia.com, bbasu@nvidia.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 24 Feb 2026 09:27:14 +0000, Sumit Gupta wrote: > > The counters_read_on_cpu() function warns when called with IRQs > disabled to prevent deadlock in smp_call_function_single(). However, > this warning is spurious when reading counters on the current CPU, > since no IPI is needed for same CPU reads. > > Commit 12eb8f4fff24 ("cpufreq: CPPC: Update FIE arch_freq_scale in > ticks for non-PCC regs") changed the CPPC Frequency Invariance Engine > to read AMU counters directly from the scheduler tick for non-PCC > register spaces (like FFH), instead of deferring to a kthread. This > means counters_read_on_cpu() is now called with IRQs disabled from > the tick handler, triggering the warning: > > | WARNING: arch/arm64/kernel/topology.c:410 at counters_read_on_cpu > | ... > | Call trace: > | counters_read_on_cpu+0x88/0xa8 (P) > | cpc_read_ffh+0xdc/0x148 > | cpc_read+0x260/0x518 > | cppc_get_perf_ctrs+0xf0/0x398 > | __cppc_scale_freq_tick+0x4c/0x148 [cppc_cpufreq] > | cppc_scale_freq_tick+0x44/0x88 [cppc_cpufreq] > | topology_scale_freq_tick+0x34/0x58 > | sched_tick+0x58/0x300 > | update_process_times+0xcc/0x120 > | tick_nohz_handler+0xa8/0x260 > | __hrtimer_run_queues+0x154/0x360 > | hrtimer_interrupt+0xf4/0x2b0 > | arch_timer_handler_phys+0x4c/0x78 > | .... > | CPPC Cpufreq:__cppc_scale_freq_tick: failed to read perf counters > | .... > > Fix this by calling the counter read function directly for same CPU > case, bypassing smp_call_function_single(). Use get_cpu() to disable > preemption, as the counter read functions call this_cpu_has_cap() > which requires a non-preemptible context. > > Fixes: 997c021abc6e ("cpufreq: CPPC: Update FIE arch_freq_scale in ticks for non-PCC regs") > Signed-off-by: Sumit Gupta > Reviewed-by: Jie Zhan > --- > v1 -> v2: > - Rebased on v7.0-rc1 > - Updated Fixes tag to match upstream commit SHA > --- > arch/arm64/kernel/topology.c | 21 +++++++++++++++++++-- > 1 file changed, 19 insertions(+), 2 deletions(-) > > diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c > index 3fe1faab0362..c3e883e99aa0 100644 > --- a/arch/arm64/kernel/topology.c > +++ b/arch/arm64/kernel/topology.c > @@ -400,12 +400,29 @@ static inline > int counters_read_on_cpu(int cpu, smp_call_func_t func, u64 *val) > { > /* > - * Abort call on counterless CPU or when interrupts are > - * disabled - can lead to deadlock in smp sync call. > + * Abort call on counterless CPU. > */ > if (!cpu_has_amu_feat(cpu)) > return -EOPNOTSUPP; > > + /* > + * For same-CPU reads, call the function directly since no IPI > + * is needed and this is safe even with IRQs disabled. > + * Use get_cpu() to disable preemption as the counter read > + * functions call this_cpu_has_cap() which requires a > + * non-preemptible context. > + */ > + if (cpu == get_cpu()) { > + func(val); > + put_cpu(); > + return 0; > + } > + put_cpu(); A slightly more elegant way to write this would be: diff --git a/arch/arm64/kernel/topology.c b/arch/arm64/kernel/topology.c index 3fe1faab03620..83c7b346dc8cf 100644 --- a/arch/arm64/kernel/topology.c +++ b/arch/arm64/kernel/topology.c @@ -406,6 +406,13 @@ int counters_read_on_cpu(int cpu, smp_call_func_t func, u64 *val) if (!cpu_has_amu_feat(cpu)) return -EOPNOTSUPP; + scoped_guard(preempt) { + if (cpu == raw_smp_processor_id()) { + func(val); + return 0; + } + } + if (WARN_ON_ONCE(irqs_disabled())) return -EPERM; But I'm more concerned by the overall pattern of doing these things in random contexts. Going back to the original patch (997c021abc6e) that states: "However, this deferred update mechanism is unnecessary and introduces extra overhead for non-PCC register spaces (e.g. System Memory or FFH), where accessing the regs won't sleep and can be safely performed from the tick context." Clearly, the AMU registers cannot be arbitrarily accessed without blocking when accessed from one CPU to another, so either this function is never called in a cross-cpu context (and the warning should be removed), or the premises of this change are wrong. Which one is it? Thanks, M. -- Without deviation from the norm, progress is not possible.