From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 339ED213E9C; Tue, 23 Sep 2025 09:25:32 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758619532; cv=none; b=CSHm8ItP4z+aQIj7VAMQrgHMCbNWY2l7s3iziNXu6i8/UL5u7HFLUuNxh+A9lCBEhNaWihwD1QfmeOBG/CBOXC9mpwcwQhkxa6KZihLcv4/ahP4336aUFLBMwQDcC+3TIbwmfmeYkehfVEXog4o2zrFPi8ufQElDo0tfGGAcbMs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1758619532; c=relaxed/simple; bh=oc4B0P3ZekiLRNlxPYAEckM5612A/iTDWIyBYwAAZfw=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=hyX+2aebUTW52DJwYrI2FWwoxMX9zz8zXNusc0nQHPlYkNBuF+VvAFBB995wWeXQir75vcDUKCNZDFfvfpUJx+2aUL/zdbMwguPdSdBpxGwrU6yWbO/iodik9sL1+OEyyYNjiOORA0Fhln4Azml3pQr64HB7h9zipWzNz4TTMUE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=LmCzedfj; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="LmCzedfj" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 07342C4CEF5; Tue, 23 Sep 2025 09:25:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1758619532; bh=oc4B0P3ZekiLRNlxPYAEckM5612A/iTDWIyBYwAAZfw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=LmCzedfjR1TQRQJsC8eJHNSLdo8tQLzVwOfYgDWuwQ9fBDk6xw7gNdFZqid4oHmRI 39UFZ7Um2aI5z/1nMDzx4d5nIMlvkmfTD4dJsUGNiRj1bNA9qqEv9aInbZTgirMxIM rgi+N7/O+a6vzKonFe4LztLlmOxm7HZnMMHa8P8GlwEHGalbPb+K90mfKapgBYOCYo /etnkHpTNjPHBX8uKF8TyGlpVSvlUGIZfvy6gc3zvQ7ArdpuWWPKfcDNmFGl0xfIrr WsO5+/EyquYQKjG/jrCtpAnhPt9ehcUz39Tw9Wxi3V6Xb0CoTkl+6hPPQZ4VlBeuID 48q8Ry8FkMoBw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1v0zH7-00000008fg9-3QWo; Tue, 23 Sep 2025 09:25:29 +0000 Date: Tue, 23 Sep 2025 10:25:29 +0100 Message-ID: <86ecrx1px2.wl-maz@kernel.org> From: Marc Zyngier To: Priscilla Lam Cc: , , , , , , , , , , , Subject: Re: [PATCH] KVM: arm64: Implement KVM_TRANSLATE ioctl for arm64 In-Reply-To: <20250923082955.66602-1-prl@amazon.com> References: <86frcd1tp4.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: prl@amazon.com, oliver.upton@linux.dev, christoffer.dall@arm.com, dwmw@amazon.co.uk, graf@amazon.com, gurugubs@amazon.com, jgrall@amazon.co.uk, joey.gouly@arm.com, kvmarm@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, suzuki.poulose@arm.com, yuzenghui@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 23 Sep 2025 09:29:55 +0100, Priscilla Lam wrote: > > Hi Oliver and Marc, > > Thanks for the detailed feedback. > > > But at the end of the day, what do you need KVM_TRANSLATE for? This > > interface is an absolute turd that is unable to represent the bare > > minimum of the architecture (writable by whom? physical address in > > which translation regime? what about S2 translations?), and is better > > left in the "utter brain fart" category. > > Regarding motivation, this patch is intended to give a userspace vmm > the ability to handle non-ISV guest faults. The Arm Arm (DDI 0487L.b, > section B3.13.6) notes that for load/store pair faults, the syndrome > may not provide the specifics of the access that faulted. In those > cases, the vmm must manually decode the instruction to emulate it. The > introduction of KVM_CAP_ARM_NISV_TO_USER > (https://lore.kernel.org/kvm/20191120164236.29359-2-maz@kernel.org/) > seems to have anticipated that flow by allowing exits to userspace on > trapped NISV instructions. What is still missing is a reliable way for > userspace to query VA->IPA translations in order to complete emulation. A guest doing this is a sure indication that it is completely broken, and will fail on actual HW, because it clearly ignores small insignificant details such as *ordering*. My other question still remains: why can't you perform this page table walk in userspace? It is actually much safer to do so because you can stop other vcpus while inspecting the PTs, and avoid a vcpu playing tricks behind your back -- something the in-kernel PTW doesn't try to avoid. Thanks, M. -- Without deviation from the norm, progress is not possible.