From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 45BFEC77B72 for ; Fri, 14 Apr 2023 11:26:00 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229805AbjDNLZ7 (ORCPT ); Fri, 14 Apr 2023 07:25:59 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:56078 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229476AbjDNLZ4 (ORCPT ); Fri, 14 Apr 2023 07:25:56 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9A7A910F2 for ; Fri, 14 Apr 2023 04:25:55 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 34CE9646EF for ; Fri, 14 Apr 2023 11:25:55 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 96366C433EF; Fri, 14 Apr 2023 11:25:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1681471554; bh=XFBlMOuCo4+PbzTxFmrpNsgf0hWfPNLySwQG3Sw3a94=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=pBRmthrIR5xCJG02+D4Fg7Zt+RgvmA18HL3SU3hNNcXieDwzqg5F0XmjvuXasxEnV CDtm2aAkiOjZQPjnzsCNkPPa7hF5gV8SmTHQRlcqvJ2WGWTz+nEqE+35MHbMPyU+i/ wbJ3C+iz/MqhnCMoOee6XQaODHeGuiv+ibcT3SLlZB3+X6sULWrotNMV9R9Fy8BU1k 69Qq5Kq4V1O+FqmjYrzNKXv9VRJtY3omSwdBmJiHdLFBNJJK1KqGjXWIS43fjOrNsp BDkht7tJPXRGWWUkWEHnL60faTpPj/iAGeG19cgXBjJyzxLA8+VBRc1xpYhSTTxDy6 hdOa6ebWBXSyQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pnHYu-008Kkg-8c; Fri, 14 Apr 2023 12:25:52 +0100 Date: Fri, 14 Apr 2023 12:25:51 +0100 Message-ID: <86edomln7k.wl-maz@kernel.org> From: Marc Zyngier To: Yipeng Zou Cc: , , , , , , , , , James Gowans Subject: Re: [RFC PATCH] genirq: introduce handle_fasteoi_edge_irq flow handler In-Reply-To: <20230310101417.1081434-1-zouyipeng@huawei.com> References: <20230310101417.1081434-1-zouyipeng@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zouyipeng@huawei.com, tglx@linutronix.de, samuel@sholland.org, oleksandr_tyshchenko@epam.com, andy.shevchenko@gmail.com, apatel@ventanamicro.com, lvjianmin@loongson.cn, linux-kernel@vger.kernel.org, chris.zjh@huawei.com, liaochang1@huawei.com, jgowans@amazon.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Fri, 10 Mar 2023 10:14:17 +0000, Yipeng Zou wrote: > > Recently, We have a LPI migration issue on the ARM SMP platform. > > For example, NIC device generates MSI and sends LPI to CPU0 via ITS, > meanwhile irqbalance running on CPU1 set irq affinity of NIC to CPU1, > the next interrupt will be sent to CPU2, due to the state of irq is > still in progress, kernel does not end up performing irq handler on > CPU2, which results in some userland service timeouts, the sequence > of events is shown as follows: > > NIC CPU0 CPU1 > > Generate IRQ#1 READ_IAR > Lock irq_desc > Set IRQD_IN_PROGRESS > Unlock irq_desc > Lock irq_desc > Change LPI Affinity > Unlock irq_desc > Call irq_handler > Generate IRQ#2 > READ_IAR > Lock irq_desc > Check IRQD_IN_PROGRESS > Unlock irq_desc > Return from interrupt#2 > Lock irq_desc > Clear IRQD_IN_PROGRESS > Unlock irq_desc > return from interrupt#1 > > For this scenario, The IRQ#2 will be lost. This does cause some exceptions. Please see my reply to James at [1]. I'd appreciate if you could give that patch a go, which I expect to be a better avenue to fix what is effectively a GIC architecture defect. Thanks, M. [1] https://lore.kernel.org/all/86pm89kyyt.wl-maz@kernel.org/ -- Without deviation from the norm, progress is not possible.