From: Marc Zyngier <maz@kernel.org>
To: Zenghui Yu <yuzenghui@huawei.com>
Cc: <kvmarm@lists.cs.columbia.edu>, <linux-kernel@vger.kernel.org>,
Eric Auger <eric.auger@redhat.com>,
James Morse <james.morse@arm.com>,
Julien Thierry <julien.thierry.kdev@gmail.com>,
Suzuki K Poulose <suzuki.poulose@arm.com>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Lorenzo Pieralisi <lorenzo.pieralisi@arm.com>,
"Andrew Murray" <Andrew.Murray@arm.com>,
Jayachandran C <jnair@marvell.com>,
"Robert Richter" <rrichter@marvell.com>
Subject: Re: [PATCH v2 09/36] irqchip/gic-v3: Add GICv4.1 VPEID size discovery
Date: Fri, 01 Nov 2019 15:13:37 +0000 [thread overview]
Message-ID: <86eeyry6hq.wl-maz@kernel.org> (raw)
In-Reply-To: <ec979d9b-cfe8-bfd8-fc4c-c41a602b2494@huawei.com>
On Thu, 31 Oct 2019 12:02:24 +0000,
Zenghui Yu <yuzenghui@huawei.com> wrote:
>
> Hi Marc,
>
> On 2019/10/27 22:42, Marc Zyngier wrote:
> > While GICv4.0 mandates 16 bit worth of VPEIDs, GICv4.1 allows smaller
> > implementations to be built. Add the required glue to dynamically
> > compute the limit.
> >
> > Signed-off-by: Marc Zyngier <maz@kernel.org>
> > ---
> > drivers/irqchip/irq-gic-v3-its.c | 11 ++++++++++-
> > drivers/irqchip/irq-gic-v3.c | 3 +++
> > include/linux/irqchip/arm-gic-v3.h | 5 +++++
> > 3 files changed, 18 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c
> > index 94c9c2e9f917..40912b3fb0e1 100644
> > --- a/drivers/irqchip/irq-gic-v3-its.c
> > +++ b/drivers/irqchip/irq-gic-v3-its.c
> > @@ -121,7 +121,16 @@ struct its_node {
> > #define ITS_ITT_ALIGN SZ_256
> > /* The maximum number of VPEID bits supported by VLPI commands
> > */
> > -#define ITS_MAX_VPEID_BITS (16)
> > +#define ITS_MAX_VPEID_BITS \
> > + ({ \
> > + int nvpeid = 16; \
> > + if (gic_rdists->has_rvpeid && \
> > + gic_rdists->gicd_typer2 & GICD_TYPER2_VIL) \
> > + nvpeid = 1 + (gic_rdists->gicd_typer2 & \
> > + GICD_TYPER2_VID); \
>
> Does it make sense to let nvpeid not more than 16 here? As the spec says
> "Values above 0x0F are RESERVED". But I don't know why should we have
> this restriction ;-)
This is something that Andrew raised in the previous version. My take
on this is that properly implemented HW should give us something that
matches the spec (in the 0-15 range), and I don't think that guarding
against that is useful at this stage.
My understanding is that once the architecture allows using the 16-31
range, we'll either use it directly because it is just a natural
extension to the existing range, or they mean something different
altogether and we'll get a new discovery bit somewhere.
> Either way,
>
> Reviewed-by: Zenghui Yu <yuzenghui@huawei.com>
Thanks,
M.
--
Jazz is not dead, it just smells funny.
next prev parent reply other threads:[~2019-11-01 15:13 UTC|newest]
Thread overview: 79+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-10-27 14:41 [PATCH v2 00/36] irqchip/gic-v4: GICv4.1 architecture support Marc Zyngier
2019-10-27 14:41 ` [PATCH v2 01/36] KVM: arm64: vgic-v4: Move the GICv4 residency flow to be driven by vcpu_load/put Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 02/36] irqchip/gic-v3-its: Factor out wait_for_syncr primitive Marc Zyngier
2019-10-28 9:20 ` Zenghui Yu
2019-11-20 13:21 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 03/36] irqchip/gic-v3-its: Allow LPI invalidation via the DirectLPI interface Marc Zyngier
2019-10-31 8:49 ` Zenghui Yu
2019-11-01 13:26 ` Marc Zyngier
2019-11-05 10:30 ` Zenghui Yu
2019-11-05 12:12 ` Marc Zyngier
2019-11-20 13:21 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 04/36] irqchip/gic-v3-its: Make is_v4 use a TYPER copy Marc Zyngier
2019-10-28 9:34 ` Zenghui Yu
2019-10-28 10:52 ` Marc Zyngier
2019-11-20 13:21 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 05/36] irqchip/gic-v3-its: Kill its->ite_size and use TYPER copy instead Marc Zyngier
2019-10-28 9:40 ` Zenghui Yu
2019-11-20 13:21 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 06/36] irqchip/gic-v3-its: Kill its->device_ids " Marc Zyngier
2019-10-31 6:33 ` Zenghui Yu
2019-10-31 8:30 ` Marc Zyngier
2019-10-31 9:08 ` Zenghui Yu
2019-11-20 13:21 ` [tip: irq/core] " tip-bot2 for Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 07/36] irqchip/gic-v3-its: Add get_vlpi_map() helper Marc Zyngier
2019-10-31 3:54 ` Zenghui Yu
2019-11-20 13:21 ` [tip: irq/core] irqchip/gic-v3-its: Add its_vlpi_map helpers tip-bot2 for Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 08/36] irqchip/gic-v3: Detect GICv4.1 supporting RVPEID Marc Zyngier
2019-10-31 11:34 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 09/36] irqchip/gic-v3: Add GICv4.1 VPEID size discovery Marc Zyngier
2019-10-31 12:02 ` Zenghui Yu
2019-11-01 15:13 ` Marc Zyngier [this message]
2019-10-27 14:42 ` [PATCH v2 10/36] irqchip/gic-v3: Workaround Cavium TX1 erratum when reading GICD_TYPER2 Marc Zyngier
2020-03-15 9:55 ` [tip: irq/urgent] irqchip/gic-v3: Workaround Cavium erratum 38539 " tip-bot2 for Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 11/36] irqchip/gic-v4.1: VPE table (aka GICR_VPROPBASER) allocation Marc Zyngier
2019-12-24 7:10 ` Zenghui Yu
2019-12-24 9:19 ` Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 12/36] irqchip/gic-v4.1: Implement the v4.1 flavour of VMAPP Marc Zyngier
2019-11-01 10:58 ` Zenghui Yu
2019-11-13 8:02 ` Zenghui Yu
2019-11-13 9:47 ` Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 13/36] irqchip/gic-v4.1: Don't use the VPE proxy if RVPEID is set Marc Zyngier
2019-11-01 11:05 ` Zenghui Yu
2019-12-18 14:39 ` Marc Zyngier
2019-12-19 3:05 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 14/36] irqchip/gic-v4.1: Implement the v4.1 flavour of VMOVP Marc Zyngier
2019-11-01 11:10 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 15/36] irqchip/gic-v4.1: Plumb skeletal VPE irqchip Marc Zyngier
2019-11-01 11:13 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 16/36] irqchip/gic-v4.1: Add mask/unmask doorbell callbacks Marc Zyngier
2019-11-01 11:23 ` Zenghui Yu
2019-12-18 15:06 ` Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 17/36] irqchip/gic-v4.1: Add VPE residency callback Marc Zyngier
2019-11-01 11:34 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 18/36] irqchip/gic-v4.1: Add VPE eviction callback Marc Zyngier
2019-11-01 11:39 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 19/36] irqchip/gic-v4.1: Add VPE INVALL callback Marc Zyngier
2019-11-01 11:51 ` Zenghui Yu
2019-12-18 14:18 ` Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 20/36] irqchip/gic-v4.1: Suppress per-VLPI doorbell Marc Zyngier
2019-11-01 12:17 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 21/36] irqchip/gic-v4.1: Allow direct invalidation of VLPIs Marc Zyngier
2019-11-01 12:30 ` Zenghui Yu
2019-10-27 14:42 ` [PATCH v2 22/36] irqchip/gic-v4.1: Advertise support v4.1 to KVM Marc Zyngier
2019-11-01 12:55 ` Zenghui Yu
2019-12-18 14:48 ` Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 23/36] irqchip/gic-v4.1: Map the ITS SGIR register page Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 24/36] irqchip/gic-v4.1: Plumb skeletal VSGI irqchip Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 25/36] irqchip/gic-v4.1: Add initial SGI configuration Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 26/36] irqchip/gic-v4.1: Plumb mask/unmask SGI callbacks Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 27/36] irqchip/gic-v4.1: Plumb get/set_irqchip_state " Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 28/36] irqchip/gic-v4.1: Plumb set_vcpu_affinity " Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 29/36] irqchip/gic-v4.1: Move doorbell management to the GICv4 abstraction layer Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 30/36] irqchip/gic-v4.1: Add VSGI allocation/teardown Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 31/36] irqchip/gic-v4.1: Add VSGI property setup Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 32/36] irqchip/gic-v4.1: Eagerly vmap vPEs Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 33/36] KVM: arm64: GICv4.1: Let doorbells be auto-enabled Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 34/36] KVM: arm64: GICv4.1: Add direct injection capability to SGI registers Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 35/36] KVM: arm64: GICv4.1: Configure SGIs as HW interrupts Marc Zyngier
2019-10-27 14:42 ` [PATCH v2 36/36] KVM: arm64: GICv4.1: Expose HW-based SGIs in debugfs Marc Zyngier
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=86eeyry6hq.wl-maz@kernel.org \
--to=maz@kernel.org \
--cc=Andrew.Murray@arm.com \
--cc=eric.auger@redhat.com \
--cc=james.morse@arm.com \
--cc=jason@lakedaemon.net \
--cc=jnair@marvell.com \
--cc=julien.thierry.kdev@gmail.com \
--cc=kvmarm@lists.cs.columbia.edu \
--cc=linux-kernel@vger.kernel.org \
--cc=lorenzo.pieralisi@arm.com \
--cc=rrichter@marvell.com \
--cc=suzuki.poulose@arm.com \
--cc=tglx@linutronix.de \
--cc=yuzenghui@huawei.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).