Re: [PATCH 2/4 v3] x86: AMD: Add hardware-enforced cache coherency as a CPUID feature

[Tom Lendacky <thomas.lendacky@amd.com>]

On 9/11/20 4:33 PM, Borislav Petkov wrote:
> + Tom.
> 
> On Fri, Sep 11, 2020 at 07:25:59PM +0000, Krish Sadhukhan wrote:
>> +#define X86_FEATURE_HW_CACHE_COHERENCY (11*32+ 7) /* AMD hardware-enforced cache coherency */
> 
> so before you guys paint the bikeshed all kinds of colors :), Tom (CCed)
> is digging out the official name. (If it is even uglier, we might keep
> on bikeshedding...).

I believe the official name is something like CoherencyEnforced. Since 
it's under the 0x8000001f leaf (AMD Secure Encryption), it means that 
coherency is enforced between the same physical address when referenced 
with or without the encryption bit (bare metal or in a guest).

So I kind of like the X86_FEATURE_SME_COHERENT suggestion by Dave, even if 
it also applies to SEV.

Thanks,
Tom

> 
> Once you have that, add the "" after the comment - like
> X86_FEATURE_FENCE_SWAPGS_USER, for example, so that it doesn't show in
> /proc/cpuinfo as luserspace doesn't care about hw coherency between enc
> memory.
> 
> Thx.
>