Re: [PATCH 1/3] ampere/arm64: Add a fixup handler for alignment faults in aarch64 code

[D Scott Phillips <scott@os.amperecomputing.com>]

Alex Bennée <alex.bennee@linaro.org> writes:

> From: D Scott Phillips <scott@os.amperecomputing.com>
>
> A later patch will hand out Device memory in some cases to code
> which expects a Normal memory type, as an errata workaround.
> Unaligned accesses to Device memory will fault though, so here we
> add a fixup handler to emulate faulting accesses, at a performance
> penalty.
>
> Many of the instructions in the Loads and Stores group are supported,
> but these groups are not handled here:
>
>  * Advanced SIMD load/store multiple structures
>  * Advanced SIMD load/store multiple structures (post-indexed)
>  * Advanced SIMD load/store single structure
>  * Advanced SIMD load/store single structure (post-indexed)

Hi Alex, I'm keeping my version of these patches here:

https://github.com/AmpereComputing/linux-ampere-altra-erratum-pcie-65

It looks like the difference to the version you've harvested is that
I've since added handling for these load/store types:

Advanced SIMD load/store multiple structure
Advanced SIMD load/store multiple structure (post-indexed)
Advanced SIMD load/store single structure
Advanced SIMD load/store single structure (post-indexed)

I've never sent these patches because in my opinion there's too much
complexity to maintain upstream for this workaround, though now they're
here so we can have that conversation.

Finally, I think a better approach overall would have been to have
device memory mapping in the stage 2 page table, then booting with pkvm
would have this workaround for both the host and guests. I don't think
that approach changes the fact that there's too much complexity here.