From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A9B9B21117; Thu, 4 Jan 2024 11:34:52 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="knP3uavG" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 28144C433C8; Thu, 4 Jan 2024 11:34:52 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1704368092; bh=2P/Mc4Boujf9+C81JhTvvl3flMRtd8Fdmy/qH4BFF3Y=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=knP3uavGDcmbaVzvhcK37L7HMxE3IxEifdUAoAK1EXKwu1Mr8Kwwkc3B3KR/aA6vq qfTF+4sh6PNmG4YLL6Sf8vObYJUdf939jt0AcboW3HHWn9TZHS9CtFBtpCbLn+eReJ ObtpD9yb/ybzVkfDxkutIAMpaykgXL4bHbkV8nD64r8npOclTTNwK4yf3+ToWy3cbU 0PUkc2xQFmTiWpi1Ncy/ciEVUJzVueqb3RibvcglTlpzmF24HmcDKAGomt9/Cr6Tmc j5gCbrGiN9Ggi67IQGox+AeZKlnJTV/1vMDGfnhM1pq71m1HtORqvU+dR0SQ068QzT zmP5jBXzap12A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rLLzt-008mUH-Ky; Thu, 04 Jan 2024 11:34:49 +0000 Date: Thu, 04 Jan 2024 11:34:48 +0000 Message-ID: <86h6jt9vs7.wl-maz@kernel.org> From: Marc Zyngier To: "Rafael J. Wysocki" Cc: Lorenzo Pieralisi , linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, Mark Rutland , Robin Murphy , Fang Xiang , Robert Moore Subject: Re: [PATCH v4 0/3] irqchip/gic-v3: Enable non-coherent GIC designs probing In-Reply-To: References: <20230905104721.52199-1-lpieralisi@kernel.org> <20231227110038.55453-1-lpieralisi@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: rafael@kernel.org, lpieralisi@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-acpi@vger.kernel.org, acpica-devel@lists.linux.dev, mark.rutland@arm.com, robin.murphy@arm.com, fangxiang3@xiaomi.com, robert.moore@intel.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 03 Jan 2024 13:43:16 +0000, "Rafael J. Wysocki" wrote: >=20 > On Wed, Dec 27, 2023 at 12:00=E2=80=AFPM Lorenzo Pieralisi > wrote: > > > > This series is v4 of previous series: > > > > v3: https://lore.kernel.org/all/20231006125929.48591-1-lpieralisi@kerne= l.org > > v2: https://lore.kernel.org/all/20230906094139.16032-1-lpieralisi@kerne= l.org > > v1: https://lore.kernel.org/all/20230905104721.52199-1-lpieralisi@kerne= l.org > > > > v3 -> v4: > > - Dropped patches [1-3], already merged > > - Added Linuxized ACPICA changes accepted upstream > > - Rebased against v6.7-rc3 > > > > v2 -> v3: > > - Added ACPICA temporary changes and ACPI changes to implement > > ECR https://bugzilla.tianocore.org/show_bug.cgi?id=3D4557 > > - ACPI changes are for testing purposes - subject to ECR code > > first approval > > > > v1 -> v2: > > - Updated DT bindings as per feedback > > - Updated patch[2] to use GIC quirks infrastructure > > > > Original cover letter > > --- > > The GICv3 architecture specifications provide a means for the > > system programmer to set the shareability and cacheability > > attributes the GIC components (redistributors and ITSes) use > > to drive memory transactions. > > > > Albeit the architecture give control over shareability/cacheability > > memory transactions attributes (and barriers), it is allowed to > > connect the GIC interconnect ports to non-coherent memory ports > > on the interconnect, basically tying off shareability/cacheability > > "wires" and de-facto making the redistributors and ITSes non-coherent > > memory observers. > > > > This series aims at starting a discussion over a possible solution > > to this problem, by adding to the GIC device tree bindings the > > standard dma-noncoherent property. The GIC driver uses the property > > to force the redistributors and ITSes shareability attributes to > > non-shareable, which consequently forces the driver to use CMOs > > on GIC memory tables. > > > > On ARM DT DMA is default non-coherent, so the GIC driver can't rely > > on the generic DT dma-coherent/non-coherent property management layer > > (of_dma_is_coherent()) which would default all GIC designs in the field > > as non-coherent; it has to rely on ad-hoc dma-noncoherent property hand= ling. > > > > When a consistent approach is agreed upon for DT an equivalent binding = will > > be put forward for ACPI based systems. > > > > Lorenzo Pieralisi (3): > > ACPICA: MADT: Add GICC online capable bit handling > > ACPICA: MADT: Add new MADT GICC/GICR/ITS non-coherent flags handling > > irqchip/gic-v3: Enable non-coherent redistributors/ITSes ACPI probing > > > > drivers/acpi/processor_core.c | 21 +++++++++++++++++++++ > > drivers/irqchip/irq-gic-common.h | 8 ++++++++ > > drivers/irqchip/irq-gic-v3-its.c | 4 ++++ > > drivers/irqchip/irq-gic-v3.c | 9 +++++++++ > > include/acpi/actbl2.h | 12 ++++++++++-- > > include/linux/acpi.h | 3 +++ > > 6 files changed, 55 insertions(+), 2 deletions(-) > > > > -- >=20 > I can apply the first 2 patches, but I would need an ACK for the 3rd one. >=20 > Alternatively, feel free to add >=20 > Acked-by: Rafael J. Wysocki >=20 > to the first 2 patches and route them via ARM64. Thanks for that. I have some comments on the third patch, which I'd like to see addressed beforehand. This is probably all 6.9 material anyway (nobody is affected by this so far). M. --=20 Without deviation from the norm, progress is not possible.