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Thu, 13 Mar 2025 17:34:47 +0000 Date: Thu, 13 Mar 2025 17:34:46 +0000 Message-ID: <86ikocomvd.wl-maz@kernel.org> From: Marc Zyngier To: =?UTF-8?B?TWlrb8WCYWo=?= Lenczewski Cc: ryan.roberts@arm.com, suzuki.poulose@arm.com, yang@os.amperecomputing.com, corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, akpm@linux-foundation.org, mark.rutland@arm.com, joey.gouly@arm.com, james.morse@arm.com, broonie@kernel.org, anshuman.khandual@arm.com, oliver.upton@linux.dev, ioworker0@gmail.com, baohua@kernel.org, david@redhat.com, jgg@ziepe.ca, shameerali.kolothum.thodi@huawei.com, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev Subject: Re: [PATCH v3 1/3] arm64: Add BBM Level 2 cpu feature In-Reply-To: <20250313104111.24196-3-miko.lenczewski@arm.com> References: <20250313104111.24196-2-miko.lenczewski@arm.com> <20250313104111.24196-3-miko.lenczewski@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miko.lenczewski@arm.com, ryan.roberts@arm.com, suzuki.poulose@arm.com, yang@os.amperecomputing.com, corbet@lwn.net, catalin.marinas@arm.com, will@kernel.org, jean-philippe@linaro.org, robin.murphy@arm.com, joro@8bytes.org, akpm@linux-foundation.org, mark.rutland@arm.com, joey.gouly@arm.com, james.morse@arm.com, broonie@kernel.org, anshuman.khandual@arm.com, oliver.upton@linux.dev, ioworker0@gmail.com, baohua@kernel.org, david@redhat.com, jgg@ziepe.ca, shameerali.kolothum.thodi@huawei.com, nicolinc@nvidia.com, mshavit@google.com, jsnitsel@redhat.com, smostafa@google.com, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, iommu@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 13 Mar 2025 10:41:10 +0000, Miko=C5=82aj Lenczewski wrote: >=20 > diff --git a/arch/arm64/kernel/pi/idreg-override.c b/arch/arm64/kernel/pi= /idreg-override.c > index c6b185b885f7..9728faa10390 100644 > --- a/arch/arm64/kernel/pi/idreg-override.c > +++ b/arch/arm64/kernel/pi/idreg-override.c > @@ -209,6 +209,7 @@ static const struct ftr_set_desc sw_features __prel64= _initconst =3D { > FIELD("nokaslr", ARM64_SW_FEATURE_OVERRIDE_NOKASLR, NULL), > FIELD("hvhe", ARM64_SW_FEATURE_OVERRIDE_HVHE, hvhe_filter), > FIELD("rodataoff", ARM64_SW_FEATURE_OVERRIDE_RODATA_OFF, NULL), > + FIELD("nobbml2", ARM64_SW_FEATURE_OVERRIDE_NOBBML2, NULL), > {} > }, > }; > @@ -246,6 +247,7 @@ static const struct { > { "rodata=3Doff", "arm64_sw.rodataoff=3D1" }, > { "arm64.nolva", "id_aa64mmfr2.varange=3D0" }, > { "arm64.no32bit_el0", "id_aa64pfr0.el0=3D1" }, > + { "arm64.nobbml2", "arm64_sw.nobbml2=3D1" }, Why is that a SW feature? This looks very much like a HW feature to me, and you should instead mask out ID_AA64MMFR2_EL1.BBM, and be done with it. Something like: diff --git a/arch/arm64/kernel/pi/idreg-override.c b/arch/arm64/kernel/pi/i= dreg-override.c index c6b185b885f70..803a0c99f7b46 100644 --- a/arch/arm64/kernel/pi/idreg-override.c +++ b/arch/arm64/kernel/pi/idreg-override.c @@ -102,6 +102,7 @@ static const struct ftr_set_desc mmfr2 __prel64_initcon= st =3D { .override =3D &id_aa64mmfr2_override, .fields =3D { FIELD("varange", ID_AA64MMFR2_EL1_VARange_SHIFT, mmfr2_varange_filter), + FIELD("bbm", ID_AA64MMFR2_EL1_BBM_SHIFT, NULL), {} }, }; @@ -246,6 +247,7 @@ static const struct { { "rodata=3Doff", "arm64_sw.rodataoff=3D1" }, { "arm64.nolva", "id_aa64mmfr2.varange=3D0" }, { "arm64.no32bit_el0", "id_aa64pfr0.el0=3D1" }, + { "arm64.nobbml2", "id_aa64mmfr2.bbm=3D0" }, }; =20 static int __init parse_hexdigit(const char *p, u64 *v) Thanks, M. --=20 Without deviation from the norm, progress is not possible.