From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 64D2FCDB465 for ; Thu, 19 Oct 2023 12:41:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1345662AbjJSMlb (ORCPT ); Thu, 19 Oct 2023 08:41:31 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44512 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1345661AbjJSMl2 (ORCPT ); Thu, 19 Oct 2023 08:41:28 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 0960611B for ; Thu, 19 Oct 2023 05:41:26 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 8D140C433C8; Thu, 19 Oct 2023 12:41:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697719285; bh=aKRs5E3FftfpY1edtDAbgzWd1N+ksQI8GIisTJHvRUw=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=MEDZAeoomE8HgLdxN/nRHLsHINrWv9An0j1RAD59kW6F3ska5LHG+HZmjX2vs8Jjc bX6RW49ofYDmQ2cLGn+yVG1b9Qt6DOFVUHMBqj0cnB7z9BOlpl1gULikXPp4h2q1by S4KZRz/uzOh/0Xvxwc/VHP/PioxonAMfvxS1d/m2JPMlTwdGIhvxzb5lwA+ZPWL+Ps 2/jXg/ZtrPVBeOjPu0op++8B/U08+x1pKomAtWbC+MajZUf+WjHpZei+nSHUpXdRj9 S0612urF0re7uj2121YR2hO5SHlGxYgmv2+uY4QrHLtyzSLLF31WgBrHKiCZ/cUoQ7 hLo08zdbTmp5w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qtSL0-005koX-1H; Thu, 19 Oct 2023 13:41:18 +0100 Date: Thu, 19 Oct 2023 13:41:17 +0100 Message-ID: <86il72n5si.wl-maz@kernel.org> From: Marc Zyngier To: Miguel Luis Cc: Catalin Marinas , Will Deacon , Oliver Upton , James Morse , Suzuki K Poulose , Zenghui Yu , Eric Auger , Jing Zhang , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v4 3/3] arm64/kvm: Fine grain _EL2 system registers list that affect nested virtualization In-Reply-To: <20231016111743.30331-4-miguel.luis@oracle.com> References: <20231016111743.30331-1-miguel.luis@oracle.com> <20231016111743.30331-4-miguel.luis@oracle.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: miguel.luis@oracle.com, catalin.marinas@arm.com, will@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, eric.auger@redhat.com, jingzhangos@google.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, kvmarm@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 16 Oct 2023 12:17:42 +0100, Miguel Luis wrote: > > Implement a fine grained approach in the _EL2 sysreg ranges. > > Fixes: d0fc0a2519a6 ("KVM: arm64: nv: Add trap forwarding for HCR_EL2") > Reviewed-by: Eric Auger > Signed-off-by: Miguel Luis > --- > arch/arm64/kvm/emulate-nested.c | 89 ++++++++++++++++++++++++++++++--- > 1 file changed, 83 insertions(+), 6 deletions(-) > > diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c > index 9ced1bf0c2b7..3a7d4003fc2b 100644 > --- a/arch/arm64/kvm/emulate-nested.c > +++ b/arch/arm64/kvm/emulate-nested.c > @@ -648,15 +648,92 @@ static const struct encoding_to_trap_config encoding_to_cgt[] __initconst = { > SR_TRAP(SYS_APGAKEYLO_EL1, CGT_HCR_APK), > SR_TRAP(SYS_APGAKEYHI_EL1, CGT_HCR_APK), > /* All _EL2 registers */ > - SR_RANGE_TRAP(sys_reg(3, 4, 0, 0, 0), > - sys_reg(3, 4, 3, 15, 7), CGT_HCR_NV), > + SR_TRAP(SYS_BRBCR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VPIDR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VMPIDR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_SCTLR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ACTLR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_SCTLR2_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_HCR_EL2, > + SYS_HCRX_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_SMPRIMAP_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_SMCR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_SDER32_EL2, CGT_HCR_NV), No. This is a *secure* register. How could it be trapped? > + SR_RANGE_TRAP(SYS_TTBR0_EL2, > + SYS_TCR2_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VTTBR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VTCR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VNCR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VSTTBR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VSTCR_EL2, CGT_HCR_NV), Secure registers. > + SR_TRAP(SYS_DACR32_EL2, CGT_HCR_NV), This only exists if EL1 is AArch32 capable. Which contradicts the basic principle that we don't support AArch32 with NV. Why would you want to forward such a trap? > + SR_RANGE_TRAP(SYS_HDFGRTR_EL2, > + SYS_HAFGRTR_EL2, CGT_HCR_NV), > /* Skip the SP_EL1 encoding... */ > SR_TRAP(SYS_SPSR_EL2, CGT_HCR_NV), > SR_TRAP(SYS_ELR_EL2, CGT_HCR_NV), > - SR_RANGE_TRAP(sys_reg(3, 4, 4, 1, 1), > - sys_reg(3, 4, 10, 15, 7), CGT_HCR_NV), > - SR_RANGE_TRAP(sys_reg(3, 4, 12, 0, 0), > - sys_reg(3, 4, 14, 15, 7), CGT_HCR_NV), > + /* SPSR_irq, SPSR_abt, SPSR_und, SPSR_fiq */ > + SR_RANGE_TRAP(sys_reg(3, 4, 4, 3, 0), > + sys_reg(3, 4, 4, 3, 3), CGT_HCR_NV), > + SR_TRAP(SYS_IFSR32_EL2, CGT_HCR_NV), Again: AArch32 related register. The spec is very clear that it UNDEFs when AArch32 doesn't exist. Even the SPSR_* registers should be removed and handled as RES0 without reinjection of the trap. > + SR_TRAP(SYS_AFSR0_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_AFSR1_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ESR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VSESR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_FPEXC32_EL2, CGT_HCR_NV), AArch32. > + SR_TRAP(SYS_TFSR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_FAR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_HPFAR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_PMSCR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_MAIR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_AMAIR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_MPAMHCR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_MPAMVPMV_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_MPAM2_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_MPAMVPM0_EL2, > + SYS_MPAMVPM7_EL2, CGT_HCR_NV), > + /* > + * Note that the spec. describes a group of MEC registers > + * whose access should not trap, therefore skip the following: > + * MECID_A0_EL2, MECID_A1_EL2, MECID_P0_EL2, > + * MECID_P1_EL2, MECIDR_EL2, VMECID_A_EL2, > + * VMECID_P_EL2. > + */ > + SR_RANGE_TRAP(SYS_VBAR_EL2, > + SYS_RMR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_VDISR_EL2, CGT_HCR_NV), > + /* ICH_AP0R_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_AP0R0_EL2, > + SYS_ICH_AP0R3_EL2, CGT_HCR_NV), > + /* ICH_AP1R_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_AP1R0_EL2, > + SYS_ICH_AP1R3_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICC_SRE_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_ICH_HCR_EL2, > + SYS_ICH_EISR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_ELRSR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_ICH_VMCR_EL2, CGT_HCR_NV), > + /* ICH_LR_EL2 */ > + SR_RANGE_TRAP(SYS_ICH_LR0_EL2, > + SYS_ICH_LR15_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_CONTEXTIDR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_TPIDR_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_SCXTNUM_EL2, CGT_HCR_NV), > + /* AMEVCNTVOFF0_EL2, AMEVCNTVOFF1_EL2 */ > + SR_RANGE_TRAP(SYS_AMEVCNTVOFF0n_EL2(0), > + SYS_AMEVCNTVOFF1n_EL2(15), CGT_HCR_NV), > + /* CNT*_EL2 */ > + SR_TRAP(SYS_CNTVOFF_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_CNTPOFF_EL2, CGT_HCR_NV), > + SR_TRAP(SYS_CNTHCTL_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_CNTHP_TVAL_EL2, > + SYS_CNTHP_CVAL_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_CNTHV_TVAL_EL2, > + SYS_CNTHV_CVAL_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_CNTHVS_TVAL_EL2, > + SYS_CNTHVS_CVAL_EL2, CGT_HCR_NV), > + SR_RANGE_TRAP(SYS_CNTHPS_TVAL_EL2, > + SYS_CNTHPS_CVAL_EL2, CGT_HCR_NV), None of these secure registers can be accessed, and they will UNDEF at EL1. M. -- Without deviation from the norm, progress is not possible.