From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05088C352A1 for ; Wed, 7 Dec 2022 11:10:06 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S229896AbiLGLKE (ORCPT ); Wed, 7 Dec 2022 06:10:04 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:51834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229876AbiLGLJV (ORCPT ); Wed, 7 Dec 2022 06:09:21 -0500 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 9E5B7BD6; Wed, 7 Dec 2022 03:07:33 -0800 (PST) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 2FBF4613CA; Wed, 7 Dec 2022 11:07:33 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 81935C433D6; Wed, 7 Dec 2022 11:07:32 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1670411252; bh=WiIeLZt0fOZzoZHz8ERnvXFAGGYuewcksszBjhqzUq8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=U5ztpf6NHe8CDPtGfHUXwOnyDErDghHaVNfJwRYQWlt3iqzev4MeRM4tff/9Q5amI vhL5y7xFnQm5qoqXZDGkzwU0zceM82Y6XfmHL/sUXY32qMNNejgLHS3AUz0qwKeODR EDxH9D45LeMGFq7ExV7pgpbCFU4rBYqQHjrPrZOFzV0kSODbjSqIDAXH1HmQ1q/In6 Iqn1Cpgs5PZTvdgirHSS85uaveXD+BOQErcFNtvpSIWjhD/InIsvSfjxOGqa7aOqQo YnZTVGZsEekYTindQOhMg80Ux5fDx1uSRpQiXX65aT4DEsu04gom22Pyvf21wb30kl il9s/SkyRQ3vg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1p2sGw-00B4Vg-Dt; Wed, 07 Dec 2022 11:07:30 +0000 Date: Wed, 07 Dec 2022 11:07:29 +0000 Message-ID: <86ilinlbf2.wl-maz@kernel.org> From: Marc Zyngier To: Yinbo Zhu Cc: Huacai Chen , Jiaxun Yang , Thomas Gleixner , linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH v1] irqchip: loongson-liointc: add hierarchy irq support In-Reply-To: References: <20221207014555.22465-1-zhuyinbo@loongson.cn> <874ju7tz4r.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zhuyinbo@loongson.cn, chenhuacai@kernel.org, jiaxun.yang@flygoat.com, tglx@linutronix.de, linux-mips@vger.kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 07 Dec 2022 10:50:56 +0000, Yinbo Zhu wrote: >=20 >=20 > =E5=9C=A8 2022/12/7 16:08, Marc Zyngier =E5=86=99=E9=81=93: > > On Wed, 07 Dec 2022 01:45:55 +0000, > > Yinbo Zhu wrote: > >> When the irq of hierarchical interrupt chip was routed to liointc > >> that asked liointc driver to support hierarchy irq and this patch > >> was to add such support. > >>=20 > >> In addition, this patch only consider dts, and acpi hierarchy irq > >> support will be added later as required. > >>=20 > >> Signed-off-by: Yinbo Zhu > >> --- > >> drivers/irqchip/irq-loongson-liointc.c | 31 ++++++++++++++++++++++++= ++ > >> 1 file changed, 31 insertions(+) > >>=20 > >> diff --git a/drivers/irqchip/irq-loongson-liointc.c b/drivers/irqchip/= irq-loongson-liointc.c > >> index 0da8716f8f24..58e43a2cd02e 100644 > >> --- a/drivers/irqchip/irq-loongson-liointc.c > >> +++ b/drivers/irqchip/irq-loongson-liointc.c > >> @@ -177,6 +177,32 @@ static const struct irq_domain_ops acpi_irq_gc_op= s =3D { > >> .xlate =3D liointc_domain_xlate, > >> }; > >> +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY > >> +static int liointc_domain_alloc(struct irq_domain *domain, unsigned i= nt virq, > >> + unsigned int nr_irqs, void *arg) > >> +{ > >> + int i, ret; > >> + irq_hw_number_t hwirq; > >> + unsigned int type =3D IRQ_TYPE_NONE; > >> + struct irq_fwspec *fwspec =3D arg; > >> + > >> + ret =3D irq_domain_translate_twocell(domain, fwspec, &hwirq, &type); > >> + if (ret) > >> + return ret; > >> + > >> + for (i =3D 0; i < nr_irqs; i++) > >> + irq_map_generic_chip(domain, virq + i, hwirq + i); > >> + > >> + return 0; > >> +} > >> + > >> +static const struct irq_domain_ops of_irq_gc_ops =3D { > >> + .translate =3D irq_domain_translate_twocell, > >> + .alloc =3D liointc_domain_alloc, > >> + .free =3D irq_domain_free_irqs_top, > >> +}; > >> +#endif > >> + > >> static int liointc_init(phys_addr_t addr, unsigned long size, int re= vision, > >> struct fwnode_handle *domain_handle, struct device_node *node) > >> { > >> @@ -218,8 +244,13 @@ static int liointc_init(phys_addr_t addr, unsigne= d long size, int revision, > >> domain =3D irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IR= Q, > >> &acpi_irq_gc_ops, priv); > >> else > >> +#ifdef CONFIG_IRQ_DOMAIN_HIERARCHY > >> + domain =3D irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IRQ, > >> + &of_irq_gc_ops, priv); > >> +#else > >> domain =3D irq_domain_create_linear(domain_handle, LIOINTC_CHIP_IR= Q, > >> &irq_generic_chip_ops, priv); > >> +#endif > > Two things: > >=20 > > - Why do we need three calls to create the same domains depending on > > what firmware is used and kernel configuration? > yes, It depend on firmeware and kernel configuration. Read again: why do we need 3 different calls to irq_domain_create_linear when you can *indirect* them with a pointer to the correct structure? > >=20 > > - who is going to decide whether to select the > > CONFIG_IRQ_DOMAIN_HIERARCHY option? > The latest gpio driver will select=C2=A0 CONFIG_IRQ_DOMAIN_HIERARCHY Then why do we need two different behaviours? The same kernel should run everywhere. > >=20 > > I'd really like to see a statement from the Loongson folks about what > > this whole DT stuff is all about. AFAICT, the core ACPICA stuff isn't > > even fully merged (i.e. we still rely on arch-specific hacks). >=20 > The support of dts is mainly for Loongson embedded chips, such as > LoongArch Loongson-2 series SoC.=C2=A0 and it use dts to descripte device > and don't support acpi. That doesn't answer my question. Please have a *consistent* approach to your interrupt handling, and work with your ACPI colleagues. M. --=20 Without deviation from the norm, progress is not possible.