From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id A66E63101D2 for ; Tue, 2 Dec 2025 11:44:08 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764675848; cv=none; b=kaYBVfMLyjUGCs/y9iByVH5IHbwbOqBqHGDz1YwH51bBvRqsARlyl27gYljmmv0+1QD23wG955p4u3ZT60tmWHaBQnkhjRUSiazBSZJT/6iL5cTC1PS5N04ZLD4NTy+AmMmNAGr5W2II7VsPJ3Z9AJdQ65Nx4zbiOiIfQ+0ziXc= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1764675848; c=relaxed/simple; bh=b9FdZ5QADtBWpT8qFoV1Nn5I8pU0omvNUcEQuYZTncA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=R8LyCNi1sBoPrQ1vSQGYh0tEYlo2SrE2ewI2uzAOW7PWpdCW4iyrPUpa5wg9ir16gzGUcFuAVp8xzgo7gbEJPdnMzE9Ctl0IcFiBO5+E/7cDKOQw+dITkbqoG4BNcJgtu8l14Zqkb2VZXo/cGBG1dYadx+M3SVNj9l404eaP3x8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=pGCvAKg3; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="pGCvAKg3" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 3CD24C4CEF1; Tue, 2 Dec 2025 11:44:08 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1764675848; bh=b9FdZ5QADtBWpT8qFoV1Nn5I8pU0omvNUcEQuYZTncA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=pGCvAKg3G+RGQStBHv//it/RpcWPdBhYGxCkL32P0YEVi1el1Xufhd8ms1v4XQqXN QFn+wUpncny2Y822S80hTx92MqDbLWmdGDqpWYu7u9Asy0AIAUkjs9Hq1GdTqh4nCn FXeXFuoqA0xt++hjrHvnUnHXL4E6+iDkh+cvPai0RxfOFtrzPIwVejsQDtPHYsmzJM c/VtfQPSF4uO8nDe8H5VOoygQqjD2kZqTGSH3Ador/wBs3wg3zX0HLeFmarnDay8rh +dj+yQpxRTAAxGVLsTj3DFfsEBmZ4x71diQHi8IlBGTMTm5gHZbJBwWmjEGECpmTnr DlajSCkVTbugg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vQOnd-00000009tQl-3Xbe; Tue, 02 Dec 2025 11:44:05 +0000 Date: Tue, 02 Dec 2025 11:44:05 +0000 Message-ID: <86ldjlp0qi.wl-maz@kernel.org> From: Marc Zyngier To: zhuling0805 Cc: Thomas Gleixner , "linux-arm-kernel@lists.infradead.org" , "linux-kernel@vger.kernel.org" Subject: Re: [PATCH] irqchip/gic: Fix UBSAN shift-out-of-bounds in GIC helpers In-Reply-To: <2fJDwUUYdEf2_eaRa041L9xkT8RkSWFeo7euOnqMbbPhUatLlEaAvGfB6sOspDmXaxO87Eh7bQLV9UolyjbMtZBT1wB2UGypjPOo0Z-RC0Q=@proton.me> References: <2fJDwUUYdEf2_eaRa041L9xkT8RkSWFeo7euOnqMbbPhUatLlEaAvGfB6sOspDmXaxO87Eh7bQLV9UolyjbMtZBT1wB2UGypjPOo0Z-RC0Q=@proton.me> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zhuling0805@proton.me, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 02 Dec 2025 10:53:24 +0000, zhuling0805 wrote: > > Hi, > > When running a kernel built with UBSAN enabled, enabling a GPIO > controller that uses a GIC interrupt as its parent triggers several > shift-out-of-bounds warnings in the GIC helpers. > > This patch fixes the issue by using unsigned constants so that the > left shifts are well-defined and UBSAN stays quiet. Next time, please put additional notes *after* the commit message. In this case, you are simply repeating what is already in the commit message, so just sending the patch without anything else would have been better. > > Thanks, > Zhu Ling > > --- > From: Zhu Ling > Date: Tue, 2 Dec 2025 17:54:10 +0800 > Subject: [PATCH] irqchip/gic: Fix UBSAN shift-out-of-bounds in GIC helpers > > When running with UBSAN enabled, enabling a GPIO controller that uses > a GIC interrupt as its parent triggers several shift-out-of-bounds > warnings: > > UBSAN: shift-out-of-bounds in drivers/irqchip/irq-gic-common.c:50:21 > left shift of 2 by 30 places cannot be represented in type 'int' > > and similar reports in gic_poke_irq() and gic_peek_irq() in > drivers/irqchip/irq-gic-v3.c. > > These come from shifting signed integer constants. Use unsigned > constants (0x2U and 1U) so that the behavior is well-defined and the > UBSAN warnings go away. I think a better approach would be to convert all of this to primitives that are designed for bit mask generation, rather than reinventing the wheel. See below for some (untested) suggestions. > > Signed-off-by: Zhu Ling > --- > drivers/irqchip/irq-gic-common.c | 2 +- > drivers/irqchip/irq-gic-v3.c | 4 ++-- > 2 files changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-common.c b/drivers/irqchip/irq-gic-common.c > index c776f9142..d4f0afd9e 100644 > --- a/drivers/irqchip/irq-gic-common.c > +++ b/drivers/irqchip/irq-gic-common.c > @@ -48,7 +48,7 @@ void gic_enable_quirks(u32 iidr, const struct gic_quirk *quirks, > int gic_configure_irq(unsigned int irq, unsigned int type, > void __iomem *base) > { > - u32 confmask = 0x2 << ((irq % 16) * 2); > + u32 confmask = 0x2U << ((irq % 16) * 2); This really should be written as: u32 confmask = BIT(((irq % 16) * 2) + 1); > u32 confoff = (irq / 16) * 4; > u32 val, oldval; > int ret = 0; > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 3de351e66..f5226c03f 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -457,7 +457,7 @@ static int gic_peek_irq(struct irq_data *d, u32 offset) > u32 index, mask; > > offset = convert_offset_index(d, offset, &index); > - mask = 1 << (index % 32); > + mask = 1U << (index % 32); and this as BIT(index % 32). > > if (gic_irq_in_rdist(d)) > base = gic_data_rdist_sgi_base(); > @@ -473,7 +473,7 @@ static void gic_poke_irq(struct irq_data *d, u32 offset) > u32 index, mask; > > offset = convert_offset_index(d, offset, &index); > - mask = 1 << (index % 32); > + mask = 1U << (index % 32); Same here. > > if (gic_irq_in_rdist(d)) > base = gic_data_rdist_sgi_base(); Thanks, M. -- Without deviation from the norm, progress is not possible.