From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id BD84021171D for ; Wed, 9 Jul 2025 16:27:05 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752078425; cv=none; b=QmBvs8bC3BQsWaKoksddbMQbMxlzQaEh9SnsTU9LFEgrCEZOo3BWn0XnUJwPIHfvks3n7SmPBkEol7Uf9jnM4zxd3sh8u5lUd8wdAIgiTXOzwPpx4Umg/MmfuBiZNqMBuWijdNvpx5ANZctVqiHZJX3OHq9E7gQZMCF74Xwq4rU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1752078425; c=relaxed/simple; bh=58dMFpVclE1fI2hMvzz1Vk2nv1dCDMBCLxLTGsdrOYQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=HRn+baicvoi51hrraZoHMHwVHs84rwHqOtOAw85JFe5H8FeP/IRTVL1i1QR97pBYOZ4Ur52uNMNr+iJmisAGmtn6jCAMXNbZKIKX+zFVw6WwwnJx6wyPe6jTkHMn89yw1Uyj3hAY4m8jaf241Gf38HiNHgP7QYCa/B8pmbXY8oE= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=jLpaJ/bS; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="jLpaJ/bS" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 5D38CC4CEEF; Wed, 9 Jul 2025 16:27:05 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1752078425; bh=58dMFpVclE1fI2hMvzz1Vk2nv1dCDMBCLxLTGsdrOYQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=jLpaJ/bS2o2KH41C6vKrFwk685YSFSUw+YJBtaqINW+aUUcheLyFkUcLPYIUVBk7b RPyN9xDhplUAjp4YEL2TdZZ2VbHczfChb51MXJtWOd6O/hQScjhJTlrYZnQcIPOKB1 rpBoOthV1lV47h8AHeeeciha7s3k/2HIdr91KQXqLfVZ2SxrXTqA6CkXDpZndTKRJS 2r1NHotP2Pm/0X6/4uPsAoe4j+tXnGjCL+jxwpvdsIsu8NvJ4sdUbYmA+42DjMyS2y keAVyUQ3nfjWLtMq+Q0GEhGuPaYC0hAoeGzW6+Uz9bsrMqcUJJNp8jp7fc3SWaMSJs MRD7dbtZp0O4Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uZXdP-00EE2d-D3; Wed, 09 Jul 2025 17:27:03 +0100 Date: Wed, 09 Jul 2025 17:27:03 +0100 Message-ID: <86ldox9voo.wl-maz@kernel.org> From: Marc Zyngier To: Zenghui Yu Cc: , , , Subject: Re: [PATCH] irqchip/gic-v3: Fix GICD_CTLR register naming In-Reply-To: <20250709130046.1354-1-yuzenghui@huawei.com> References: <20250709130046.1354-1-yuzenghui@huawei.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: yuzenghui@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, tglx@linutronix.de, wanghaibin.wang@huawei.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 09 Jul 2025 14:00:46 +0100, Zenghui Yu wrote: > > It was incorrectly named as GICD_CTRL in a pr_info() and comments. Fix > them. > > Signed-off-by: Zenghui Yu > --- > drivers/irqchip/irq-gic-v3.c | 6 +++--- > 1 file changed, 3 insertions(+), 3 deletions(-) > > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index efc791c43d44..dbeb85677b08 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -190,12 +190,12 @@ static void __init gic_prio_init(void) > > /* > * How priority values are used by the GIC depends on two things: > - * the security state of the GIC (controlled by the GICD_CTRL.DS bit) > + * the security state of the GIC (controlled by the GICD_CTLR.DS bit) > * and if Group 0 interrupts can be delivered to Linux in the non-secure > * world as FIQs (controlled by the SCR_EL3.FIQ bit). These affect the > * way priorities are presented in ICC_PMR_EL1 and in the distributor: > * > - * GICD_CTRL.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Distributor > + * GICD_CTLR.DS | SCR_EL3.FIQ | ICC_PMR_EL1 | Distributor > * ------------------------------------------------------- > * 1 | - | unchanged | unchanged > * ------------------------------------------------------- > @@ -223,7 +223,7 @@ static void __init gic_prio_init(void) > dist_prio_nmi = __gicv3_prio_to_ns(dist_prio_nmi); > } > > - pr_info("GICD_CTRL.DS=%d, SCR_EL3.FIQ=%d\n", > + pr_info("GICD_CTLR.DS=%d, SCR_EL3.FIQ=%d\n", > cpus_have_security_disabled, > !cpus_have_group0); > } Hey, even people at ARM have made the same creative typo[1]! Acked-by: Marc Zyngier Thanks, M. [1] https://developer.arm.com/documentation/198123/0302/Appendix--Legacy-operation -- Without deviation from the norm, progress is not possible.