From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2D23EC4167B for ; Mon, 4 Dec 2023 10:00:07 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230172AbjLDJ76 (ORCPT ); Mon, 4 Dec 2023 04:59:58 -0500 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47182 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229526AbjLDJ75 (ORCPT ); Mon, 4 Dec 2023 04:59:57 -0500 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 03BA3B3 for ; Mon, 4 Dec 2023 02:00:03 -0800 (PST) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 956FFC433C8; Mon, 4 Dec 2023 10:00:02 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1701684002; bh=1YZjL/utSLEnI8q+lVNvs3ICUJloIgY8GaKf1bnCeu8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=m2+6dwq7jbUm4hkP9OHb1dIQid5INf2Ty2w8T5dEFWBL8HYwYeyzuShaHE8gR/wpm Ak4I4xjEqJxkTJWrvpCmB8CyrDWcPOpLY78Bw7smdz0LDz0kuHa4WBUeI0RlfqiEPn htTvLexodqTXO7/Ot0LeZsL9P9Bnhv85tBseik2L0N61H6jDLPArRFIaea2IAa/Ws7 4uOODhgyXR4fCZ0iwb1YBof//fad5EDO5RkCjg+R+Aim+NovV7yuy8geI9WDh5jO03 dR3oziT0pgFbQjrpn2m87P7pSoStqX0QB/vUixuZ4Wq3NPBKJSVytwAqcT8mrQcpvh Z2tHjU7adEeLw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rA5k8-001Amr-0o; Mon, 04 Dec 2023 10:00:00 +0000 Date: Mon, 04 Dec 2023 09:59:59 +0000 Message-ID: <86msuqb84g.wl-maz@kernel.org> From: Marc Zyngier To: James Clark Cc: coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, suzuki.poulose@arm.com, broonie@kernel.org, Oliver Upton , James Morse , Zenghui Yu , Catalin Marinas , Will Deacon , Mike Leach , Leo Yan , Alexander Shishkin , Anshuman Khandual , Rob Herring , Jintack Lim , Kristina Martsenko , Fuad Tabba , Akihiko Odaki , Joey Gouly , linux-kernel@vger.kernel.org Subject: Re: [PATCH v3 4/6] arm64: KVM: Add interface to set guest value for TRFCR register In-Reply-To: <20231019165510.1966367-5-james.clark@arm.com> References: <20231019165510.1966367-1-james.clark@arm.com> <20231019165510.1966367-5-james.clark@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: james.clark@arm.com, coresight@lists.linaro.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev, suzuki.poulose@arm.com, broonie@kernel.org, oliver.upton@linux.dev, james.morse@arm.com, yuzenghui@huawei.com, catalin.marinas@arm.com, will@kernel.org, mike.leach@linaro.org, leo.yan@linaro.org, alexander.shishkin@linux.intel.com, anshuman.khandual@arm.com, robh@kernel.org, jintack.lim@linaro.org, kristina.martsenko@arm.com, tabba@google.com, akihiko.odaki@daynix.com, joey.gouly@arm.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Thu, 19 Oct 2023 17:55:02 +0100, James Clark wrote: > > Add an interface for the Coresight driver to use to set the value of the > TRFCR register for the guest. This register controls the exclude > settings for trace at different exception levels, and is used to honor > the exclude_host and exclude_guest parameters from the Perf session. > This will be used to later write TRFCR_EL1 on nVHE at guest switch. For > VHE, the host trace is controlled by TRFCR_EL2 and thus we can write to > the TRFCR_EL1 immediately. Because guest writes to the register are > trapped, the value will persist and can't be modified. > > The settings must be copied to the vCPU before each run in the same > way that PMU events are, because the per-cpu struct isn't accessible in > protected mode. Then maybe we should look at a better way of sharing global data between EL1 and EL2 instead of copying stuff ad-nauseam? > > Signed-off-by: James Clark > --- > arch/arm64/include/asm/kvm_host.h | 3 +++ > arch/arm64/kvm/arm.c | 1 + > arch/arm64/kvm/debug.c | 26 ++++++++++++++++++++++++++ > 3 files changed, 30 insertions(+) > > diff --git a/arch/arm64/include/asm/kvm_host.h b/arch/arm64/include/asm/kvm_host.h > index 0f0bf8e641bd..e1852102550d 100644 > --- a/arch/arm64/include/asm/kvm_host.h > +++ b/arch/arm64/include/asm/kvm_host.h > @@ -1125,6 +1125,8 @@ void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu); > void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr); > void kvm_clr_pmu_events(u32 clr); > bool kvm_set_pmuserenr(u64 val); > +void kvm_etm_set_guest_trfcr(u64 trfcr_guest); > +void kvm_etm_update_vcpu_events(struct kvm_vcpu *vcpu); > #else > static inline void kvm_set_pmu_events(u32 set, struct perf_event_attr *attr) {} > static inline void kvm_clr_pmu_events(u32 clr) {} > @@ -1132,6 +1134,7 @@ static inline bool kvm_set_pmuserenr(u64 val) > { > return false; > } > +static inline void kvm_etm_set_guest_trfcr(u64 trfcr_guest) {} > #endif > > void kvm_vcpu_load_sysregs_vhe(struct kvm_vcpu *vcpu); > diff --git a/arch/arm64/kvm/arm.c b/arch/arm64/kvm/arm.c > index 0f717b6a9151..e4d846f2f665 100644 > --- a/arch/arm64/kvm/arm.c > +++ b/arch/arm64/kvm/arm.c > @@ -1015,6 +1015,7 @@ int kvm_arch_vcpu_ioctl_run(struct kvm_vcpu *vcpu) > kvm_vgic_flush_hwstate(vcpu); > > kvm_pmu_update_vcpu_events(vcpu); > + kvm_etm_update_vcpu_events(vcpu); > > /* > * Ensure we set mode to IN_GUEST_MODE after we disable > diff --git a/arch/arm64/kvm/debug.c b/arch/arm64/kvm/debug.c > index 20cdd40b3c42..2ab41b954512 100644 > --- a/arch/arm64/kvm/debug.c > +++ b/arch/arm64/kvm/debug.c > @@ -23,6 +23,12 @@ > > static DEFINE_PER_CPU(u64, mdcr_el2); > > +/* > + * Per CPU value for TRFCR that should be applied to any guest vcpu that may > + * run on that core in the future. > + */ > +static DEFINE_PER_CPU(u64, guest_trfcr); > + > /** > * save/restore_guest_debug_regs > * > @@ -356,3 +362,23 @@ void kvm_arch_vcpu_put_debug_state_flags(struct kvm_vcpu *vcpu) > vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRBE); > vcpu_clear_flag(vcpu, DEBUG_STATE_SAVE_TRFCR); > } > + > +void kvm_etm_set_guest_trfcr(u64 trfcr_guest) > +{ > + if (has_vhe()) > + write_sysreg_s(trfcr_guest, SYS_TRFCR_EL12); > + else > + *this_cpu_ptr(&guest_trfcr) = trfcr_guest; > +} > +EXPORT_SYMBOL_GPL(kvm_etm_set_guest_trfcr); How does the ETM code know what guests it impacts? Don't you have some per-process context already? > + > +/* > + * Updates the vcpu's view of the etm events for this cpu. Must be > + * called before every vcpu run after disabling interrupts, to ensure > + * that an interrupt cannot fire and update the structure. > + */ > +void kvm_etm_update_vcpu_events(struct kvm_vcpu *vcpu) > +{ > + if (!has_vhe() && vcpu_get_flag(vcpu, DEBUG_STATE_SAVE_TRFCR)) > + ctxt_sys_reg(&vcpu->arch.ctxt, TRFCR_EL1) = *this_cpu_ptr(&guest_trfcr); > +} Why this requirement of updating it at all times? Why can't this be done in a more lazy way, using the flags to instruct the hypervisor what and when to load it? M. -- Without deviation from the norm, progress is not possible.