From: Marc Zyngier <maz@kernel.org>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: Vijay Balakrishna <vijayb@linux.microsoft.com>,
Borislav Petkov <bp@alien8.de>, Tony Luck <tony.luck@intel.com>,
James Morse <james.morse@arm.com>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Robert Richter <rric@kernel.org>,
linux-edac@vger.kernel.org, linux-kernel@vger.kernel.org,
Tyler Hicks <code@tyhicks.com>,
Sascha Hauer <s.hauer@pengutronix.de>
Subject: Re: [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property
Date: Thu, 10 Apr 2025 08:10:18 +0100 [thread overview]
Message-ID: <86o6x4lcf9.wl-maz@kernel.org> (raw)
In-Reply-To: <319b7c65-3e2f-456b-a845-45f7a57ba2c5@kernel.org>
On Thu, 10 Apr 2025 07:00:55 +0100,
Krzysztof Kozlowski <krzk@kernel.org> wrote:
>
> On 10/04/2025 01:36, Vijay Balakrishna wrote:
> > From: Sascha Hauer <s.hauer@pengutronix.de>
> >
> > Some ARM Cortex CPUs like the A53, A57 and A72 have Error Detection And
> > Correction (EDAC) support on their L1 and L2 caches. This is implemented
> > in implementation defined registers, so usage of this functionality is
> > not safe in virtualized environments or when EL3 already uses these
> > registers. This patch adds a edac-enabled flag which can be explicitly
> > set when EDAC can be used.
>
> Can't hypervisor tell you that?
No, it can't. This is not an architecture feature, and KVM will gladly
inject an UNDEF exception if the guest tries to use this.
Which is yet another reason why this whole exercise is futile.
M.
--
Without deviation from the norm, progress is not possible.
next prev parent reply other threads:[~2025-04-10 7:10 UTC|newest]
Thread overview: 16+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-04-09 23:36 [PATCH v6 0/2] Add L1 and L2 error detection for A53, A57 and A72 Vijay Balakrishna
2025-04-09 23:36 ` [PATCH 1/2] drivers/edac: " Vijay Balakrishna
2025-04-10 20:04 ` Tyler Hicks (Microsoft)
2025-04-10 22:27 ` Vijay Balakrishna
2025-04-10 22:29 ` Vijay Balakrishna
2025-04-09 23:36 ` [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
2025-04-10 6:00 ` Krzysztof Kozlowski
2025-04-10 7:10 ` Marc Zyngier [this message]
2025-04-10 14:30 ` Tyler Hicks (Microsoft)
2025-04-10 16:23 ` Marc Zyngier
2025-04-10 16:42 ` Tyler Hicks (Microsoft)
2025-04-11 20:02 ` Borislav Petkov
2025-04-13 10:38 ` Marc Zyngier
-- strict thread matches above, loose matches on Subject: below --
2025-04-11 22:08 [v7 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Vijay Balakrishna
2025-04-11 22:08 ` [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
2025-05-05 0:27 [v8 PATCH 0/2] Add L1 and L2 error detection for A53, A57 and A72 Vijay Balakrishna
2025-05-05 0:27 ` [PATCH 2/2] dt-bindings: arm: cpus: Add edac-enabled property Vijay Balakrishna
2025-05-12 19:30 ` Rob Herring
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