[PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Anshuman Khandual]

Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
ensures that MMU stage-2 translation remain disabled. Although clearing out
VTTBR_EL2 probably should have been sufficient but adding VTCR_EL2 improves
overall safety.

Cc: Catalin Marinas <catalin.marinas@arm.com>
Cc: Will Deacon <will@kernel.org>
Cc: Marc Zyngier <maz@kernel.org>
Cc: Oliver Upton <oupton@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>
Cc: linux-arm-kernel@lists.infradead.org
Cc: linux-kernel@vger.kernel.org
Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
---
 arch/arm64/include/asm/el2_setup.h | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
index 85f4c1615472..2c88033591bb 100644
--- a/arch/arm64/include/asm/el2_setup.h
+++ b/arch/arm64/include/asm/el2_setup.h
@@ -189,6 +189,7 @@
 /* Stage-2 translation */
 .macro __init_el2_stage2
 	msr	vttbr_el2, xzr
+	msr	vtcr_el2, xzr
 .endm
 
 /* GICv3 system register access */
-- 
2.30.2

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Marc Zyngier]

On Fri, 13 Mar 2026 05:38:57 +0000,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
> ensures that MMU stage-2 translation remain disabled. Although clearing out
> VTTBR_EL2 probably should have been sufficient but adding VTCR_EL2 improves
> overall safety.

This serves no purpose whatsoever. Even the write to VTTBR_EL2 is
pointless, and writing 0 is no better than writing *any* other value.

The only thing that matters at this stage is HCR_EL2.VM, which
actually controls stage-2 translation (contrary to your above
assertion). This of course is not captured by this macro.

So what are you *really* trying to achieve?

Thanks,

	M.

-- 
Jazz isn't dead. It just smells funny.

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Anshuman Khandual]

On 13/03/26 12:55 PM, Marc Zyngier wrote:
> On Fri, 13 Mar 2026 05:38:57 +0000,
> Anshuman Khandual <anshuman.khandual@arm.com> wrote:
>>
>> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
>> ensures that MMU stage-2 translation remain disabled. Although clearing out
>> VTTBR_EL2 probably should have been sufficient but adding VTCR_EL2 improves
>> overall safety.
> 
> This serves no purpose whatsoever. Even the write to VTTBR_EL2 is
> pointless, and writing 0 is no better than writing *any* other value.
> > The only thing that matters at this stage is HCR_EL2.VM, which
> actually controls stage-2 translation (contrary to your above
> assertion). This of course is not captured by this macro.
> 
> So what are you *really* trying to achieve?

To keep VTTBR_EL2 and VTCR_EL2 cleared (and prepared) if and when
HCR_EL2_VM gets enabled. But it can be argued that these registers
need not have to be cleared now and can just be initialised before
setting up HCR_EL2_VM itself. In which case should we drop
__init_el2_stage2() entirely ?

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Marc Zyngier]

On Fri, 13 Mar 2026 07:54:04 +0000,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> On 13/03/26 12:55 PM, Marc Zyngier wrote:
> > On Fri, 13 Mar 2026 05:38:57 +0000,
> > Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> >>
> >> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
> >> ensures that MMU stage-2 translation remain disabled. Although clearing out
> >> VTTBR_EL2 probably should have been sufficient but adding VTCR_EL2 improves
> >> overall safety.
> > 
> > This serves no purpose whatsoever. Even the write to VTTBR_EL2 is
> > pointless, and writing 0 is no better than writing *any* other value.
> > > The only thing that matters at this stage is HCR_EL2.VM, which
> > actually controls stage-2 translation (contrary to your above
> > assertion). This of course is not captured by this macro.
> > 
> > So what are you *really* trying to achieve?
> 
> To keep VTTBR_EL2 and VTCR_EL2 cleared (and prepared) if and when
> HCR_EL2_VM gets enabled.

How does that prepare anything? Zero is not even a valid value for
VTCR_EL2!

> But it can be argued that these registers
> need not have to be cleared now and can just be initialised before
> setting up HCR_EL2_VM itself. In which case should we drop
> __init_el2_stage2() entirely ?

I really like how you argue one thing and its opposite in two adjacent
sentences.

"If it ain't broke, don't fix it".

	M.

-- 
Jazz isn't dead. It just smells funny.

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Marc Zyngier]

On Fri, 13 Mar 2026 07:54:04 +0000,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> But it can be argued that these registers
> need not have to be cleared now and can just be initialised before
> setting up HCR_EL2_VM itself. In which case should we drop
> __init_el2_stage2() entirely ?

And something worth thinking of: the role of VTTBR_EL2.VMID when
HCR_EL2.VM is 0.

	M.

-- 
Jazz isn't dead. It just smells funny.

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Anshuman Khandual]

On 13/03/26 1:41 PM, Marc Zyngier wrote:
> On Fri, 13 Mar 2026 07:54:04 +0000,
> Anshuman Khandual <anshuman.khandual@arm.com> wrote:
>>
>> But it can be argued that these registers
>> need not have to be cleared now and can just be initialised before
>> setting up HCR_EL2_VM itself. In which case should we drop
>> __init_el2_stage2() entirely ?
> 
> And something worth thinking of: the role of VTTBR_EL2.VMID when
> HCR_EL2.VM is 0.

Are you suggesting that VTTBR_EL2_VMID needs to be 0 even when
HCR_EL2_VM = 0 because of its corresponding TLB entries ? But
during system boot such possibilities might not really exist ?

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Marc Zyngier]

On Fri, 13 Mar 2026 08:39:46 +0000,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> 
> 
> On 13/03/26 1:41 PM, Marc Zyngier wrote:
> > On Fri, 13 Mar 2026 07:54:04 +0000,
> > Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> >>
> >> But it can be argued that these registers
> >> need not have to be cleared now and can just be initialised before
> >> setting up HCR_EL2_VM itself. In which case should we drop
> >> __init_el2_stage2() entirely ?
> > 
> > And something worth thinking of: the role of VTTBR_EL2.VMID when
> > HCR_EL2.VM is 0.
> 
> Are you suggesting that VTTBR_EL2_VMID needs to be 0 even when
> HCR_EL2_VM = 0 because of its corresponding TLB entries ? But
> during system boot such possibilities might not really exist ?

This is not a suggestion. This is an architectural requirement.

TLBs filled from the EL1&0 translation regime are always tagged by
VMID when EL2 is implemented, irrespective of HCR_EL2.VM.

	M.

-- 
Jazz isn't dead. It just smells funny.

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Mark Rutland]

On Fri, Mar 13, 2026 at 05:38:57AM +0000, Anshuman Khandual wrote:
> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
> ensures that MMU stage-2 translation remain disabled.

As Marc noted, that's not true -- whether stage 2 is enabled is governed
entirely by HCR_EL2.VM.

The only reason to initialize VTCR_EL2 here would be if some field in
VTCR_EL2 applies when stage 2 is *disabled*.

> Although clearing out VTTBR_EL2 probably should have been sufficient
> but adding VTCR_EL2 improves overall safety.

It's unhelpful to send patches like this with unclear or non-existent
rationale, and vague statements about what the patch might do. Was there
some specific reason to send this? e.g.

* Did you have any specific reason to believe that setting some field in
  VTCR_EL2 was necessary? e.g. is there some misleading documentation,
  or comment elsewhere in the kernel?

* Are you trying to fix some problem you've encountered, but haven't
  managed to debug?

* Was this purely from inspection?

Mark.

> Cc: Catalin Marinas <catalin.marinas@arm.com>
> Cc: Will Deacon <will@kernel.org>
> Cc: Marc Zyngier <maz@kernel.org>
> Cc: Oliver Upton <oupton@kernel.org>
> Cc: Mark Rutland <mark.rutland@arm.com>
> Cc: linux-arm-kernel@lists.infradead.org
> Cc: linux-kernel@vger.kernel.org
> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> ---
>  arch/arm64/include/asm/el2_setup.h | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> index 85f4c1615472..2c88033591bb 100644
> --- a/arch/arm64/include/asm/el2_setup.h
> +++ b/arch/arm64/include/asm/el2_setup.h
> @@ -189,6 +189,7 @@
>  /* Stage-2 translation */
>  .macro __init_el2_stage2
>  	msr	vttbr_el2, xzr
> +	msr	vtcr_el2, xzr
>  .endm
>  
>  /* GICv3 system register access */
> -- 
> 2.30.2
> 

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Anshuman Khandual]

On 13/03/26 3:29 PM, Mark Rutland wrote:
> On Fri, Mar 13, 2026 at 05:38:57AM +0000, Anshuman Khandual wrote:
>> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
>> ensures that MMU stage-2 translation remain disabled.
> 
> As Marc noted, that's not true -- whether stage 2 is enabled is governed
> entirely by HCR_EL2.VM.
> > The only reason to initialize VTCR_EL2 here would be if some field in
> VTCR_EL2 applies when stage 2 is *disabled*.

Understood. Something similar to VTTBR_EL2.VMID field which
gets into tagged TLB entries for EL0/EL1 translation regime
even when stage-2 is not enabled via HCR_EL2_VM.

But wondering if VTTBR_EL2.VMID gets cleaned up should not
it also be followed by a "tlbi vmalls12e1 --> dsb --> isb"
sequence to clear existing stale TLB entries ?

> 
>> Although clearing out VTTBR_EL2 probably should have been sufficient
>> but adding VTCR_EL2 improves overall safety.
> 
> It's unhelpful to send patches like this with unclear or non-existent
> rationale, and vague statements about what the patch might do. Was there

The commit message could have been more detailed and explicit
about its rationale. Although the intent here was to ensure
improved safety during S2 MMU context initialization.

> some specific reason to send this? e.g.
> 
> * Did you have any specific reason to believe that setting some field in
>   VTCR_EL2 was necessary? e.g. is there some misleading documentation,
>   or comment elsewhere in the kernel?
> 
> * Are you trying to fix some problem you've encountered, but haven't
>   managed to debug?
> 
> * Was this purely from inspection?

This was from code inspection while navigating S2 MMU context
initialization and management.

> 
> Mark.
> 
>> Cc: Catalin Marinas <catalin.marinas@arm.com>
>> Cc: Will Deacon <will@kernel.org>
>> Cc: Marc Zyngier <maz@kernel.org>
>> Cc: Oliver Upton <oupton@kernel.org>
>> Cc: Mark Rutland <mark.rutland@arm.com>
>> Cc: linux-arm-kernel@lists.infradead.org
>> Cc: linux-kernel@vger.kernel.org
>> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
>> ---
>>  arch/arm64/include/asm/el2_setup.h | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
>> index 85f4c1615472..2c88033591bb 100644
>> --- a/arch/arm64/include/asm/el2_setup.h
>> +++ b/arch/arm64/include/asm/el2_setup.h
>> @@ -189,6 +189,7 @@
>>  /* Stage-2 translation */
>>  .macro __init_el2_stage2
>>  	msr	vttbr_el2, xzr
>> +	msr	vtcr_el2, xzr
>>  .endm
>>  
>>  /* GICv3 system register access */
>> -- 
>> 2.30.2
>>

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Marc Zyngier]

On Tue, 17 Mar 2026 02:46:44 +0000,
Anshuman Khandual <anshuman.khandual@arm.com> wrote:
> 
> On 13/03/26 3:29 PM, Mark Rutland wrote:
> > On Fri, Mar 13, 2026 at 05:38:57AM +0000, Anshuman Khandual wrote:
> >> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
> >> ensures that MMU stage-2 translation remain disabled.
> > 
> > As Marc noted, that's not true -- whether stage 2 is enabled is governed
> > entirely by HCR_EL2.VM.
> > > The only reason to initialize VTCR_EL2 here would be if some field in
> > VTCR_EL2 applies when stage 2 is *disabled*.
> 
> Understood. Something similar to VTTBR_EL2.VMID field which
> gets into tagged TLB entries for EL0/EL1 translation regime
> even when stage-2 is not enabled via HCR_EL2_VM.
> 
> But wondering if VTTBR_EL2.VMID gets cleaned up should not
> it also be followed by a "tlbi vmalls12e1 --> dsb --> isb"
> sequence to clear existing stale TLB entries ?

Why? We already have a TLBI VMALLE1 whenever a CPU boots. That's all
we need, and not some random invalidation that serves no purpose as
long as S2 is *off*. When we are about to turn S2 on, we have all the
required invalidation already.

> 
> > 
> >> Although clearing out VTTBR_EL2 probably should have been sufficient
> >> but adding VTCR_EL2 improves overall safety.
> > 
> > It's unhelpful to send patches like this with unclear or non-existent
> > rationale, and vague statements about what the patch might do. Was there
> 
> The commit message could have been more detailed and explicit
> about its rationale. Although the intent here was to ensure
> improved safety during S2 MMU context initialization.
> 
> > some specific reason to send this? e.g.
> > 
> > * Did you have any specific reason to believe that setting some field in
> >   VTCR_EL2 was necessary? e.g. is there some misleading documentation,
> >   or comment elsewhere in the kernel?
> > 
> > * Are you trying to fix some problem you've encountered, but haven't
> >   managed to debug?
> > 
> > * Was this purely from inspection?
> 
> This was from code inspection while navigating S2 MMU context
> initialization and management.

I think you should start by improving your understanding of how S2
works *before* sending random patches.

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.

Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2()

[Mark Rutland]

On Tue, Mar 17, 2026 at 08:16:44AM +0530, Anshuman Khandual wrote:
> On 13/03/26 3:29 PM, Mark Rutland wrote:
> > On Fri, Mar 13, 2026 at 05:38:57AM +0000, Anshuman Khandual wrote:
> >> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which
> >> ensures that MMU stage-2 translation remain disabled.
> > 
> > As Marc noted, that's not true -- whether stage 2 is enabled is governed
> > entirely by HCR_EL2.VM.
> > > The only reason to initialize VTCR_EL2 here would be if some field in
> > VTCR_EL2 applies when stage 2 is *disabled*.
> 
> Understood. Something similar to VTTBR_EL2.VMID field which
> gets into tagged TLB entries for EL0/EL1 translation regime
> even when stage-2 is not enabled via HCR_EL2_VM.
> 
> But wondering if VTTBR_EL2.VMID gets cleaned up should not
> it also be followed by a "tlbi vmalls12e1 --> dsb --> isb"
> sequence to clear existing stale TLB entries ?

We only need to do that before they're used.

> >> Although clearing out VTTBR_EL2 probably should have been sufficient
> >> but adding VTCR_EL2 improves overall safety.
> > 
> > It's unhelpful to send patches like this with unclear or non-existent
> > rationale, and vague statements about what the patch might do. Was there
> 
> The commit message could have been more detailed and explicit
> about its rationale. Although the intent here was to ensure
> improved safety during S2 MMU context initialization.

Sorry, but "improvied safety" is meaningless unless you can express a
specific concern.

You don't appear to have done reading to understand basic concepts in
this area (e.g. *when* Stage 2 is enabled, and which system register
fields affect this), and you're wasting reviewers' time with incorrect
theories about how the architecture works, where *you* could do the
necessary work.

Please do that background reading *before* sending patches like this,
and please do not send patches without a more concrete rationale.

> > some specific reason to send this? e.g.
> > 
> > * Did you have any specific reason to believe that setting some field in
> >   VTCR_EL2 was necessary? e.g. is there some misleading documentation,
> >   or comment elsewhere in the kernel?
> > 
> > * Are you trying to fix some problem you've encountered, but haven't
> >   managed to debug?
> > 
> > * Was this purely from inspection?
> 
> This was from code inspection while navigating S2 MMU context
> initialization and management.

Ok. As above, please do background reading before sending patches like
this.

Mark.

> > Mark.
> > 
> >> Cc: Catalin Marinas <catalin.marinas@arm.com>
> >> Cc: Will Deacon <will@kernel.org>
> >> Cc: Marc Zyngier <maz@kernel.org>
> >> Cc: Oliver Upton <oupton@kernel.org>
> >> Cc: Mark Rutland <mark.rutland@arm.com>
> >> Cc: linux-arm-kernel@lists.infradead.org
> >> Cc: linux-kernel@vger.kernel.org
> >> Signed-off-by: Anshuman Khandual <anshuman.khandual@arm.com>
> >> ---
> >>  arch/arm64/include/asm/el2_setup.h | 1 +
> >>  1 file changed, 1 insertion(+)
> >>
> >> diff --git a/arch/arm64/include/asm/el2_setup.h b/arch/arm64/include/asm/el2_setup.h
> >> index 85f4c1615472..2c88033591bb 100644
> >> --- a/arch/arm64/include/asm/el2_setup.h
> >> +++ b/arch/arm64/include/asm/el2_setup.h
> >> @@ -189,6 +189,7 @@
> >>  /* Stage-2 translation */
> >>  .macro __init_el2_stage2
> >>  	msr	vttbr_el2, xzr
> >> +	msr	vtcr_el2, xzr
> >>  .endm
> >>  
> >>  /* GICv3 system register access */
> >> -- 
> >> 2.30.2
> >>
>