From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7F8AF35AC35 for ; Tue, 17 Mar 2026 09:15:59 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773738959; cv=none; b=tv0vhxmFtiV8DAhlXI10ExP+z4fCkdWmHjgJ1DkKoMo6dS2XLHkkSWPOwAXmjXK5QTmCXQG1zQ3kKEcvDmH80B0UAetyv13iwmKhTlUApbe3+h7pFDV3kPhEN4csV3M7K/cBSxwcwrPAHtU4eMgvEuEXk561KR6qPY7EctcM3tg= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1773738959; c=relaxed/simple; bh=LSTBUr70d++aqtd2i7v9HZOKnkhIvYU6wX2nJRDMMxo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=ZPfNznz6zWZIeh+ysJaj8w05D8FFRrkWvFDEBaUv+YBqOOXAe7lOpazRjamy75vTdPuCj9El4o7x1xkixEeGTIoBmbOqpeoft8ITfG15MaVH+ufhBowikcq05kTzqZ7D6IO0KUvjtReUTwcwKa+jgKJjrm06u9tYdaDQwL9hXug= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=CU9xCHKx; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="CU9xCHKx" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E3D50C2BCB0; Tue, 17 Mar 2026 09:15:58 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1773738959; bh=LSTBUr70d++aqtd2i7v9HZOKnkhIvYU6wX2nJRDMMxo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=CU9xCHKxT9iwW6uW8L8eKEEg3SUwHc0bg7BUXqPIPojKfsvOrSeD/4ELiacWUNmfF kHow0qt5YwULc/ry7z/d3psBrdaQ3KW56Sn0HYnT9dPXl7nP1b6X7L/7J9fL2rZycE 6C2w20UhRPcwkfxNXwaLp5MQFYK/bf811sXbOAu9BhMEEGl9U9vP1mn8ffrGVDinJT bCqQtuAIt27BALaN+DZt0iS49U1Br+TpxCjDB5eS2MzEVhZ+K1eb+PkiCKrsL+qo6n VOFS0MbrLw1xHnbbsHUIcLit+XU7fRei+xYnYTHJgiJGLC6Ycl96zxE5Tm4Xil+A7D 6mV30RDTSa77A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w2QWq-00000002ket-3RQe; Tue, 17 Mar 2026 09:15:56 +0000 Date: Tue, 17 Mar 2026 09:15:56 +0000 Message-ID: <86pl526ckz.wl-maz@kernel.org> From: Marc Zyngier To: Anshuman Khandual Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Oliver Upton , linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: Clear VTCR_EL2 in __init_el2_stage2() In-Reply-To: <3dc3f358-7f4a-4950-b8f7-f3b3c284166b@arm.com> References: <20260313053857.1277828-1-anshuman.khandual@arm.com> <3dc3f358-7f4a-4950-b8f7-f3b3c284166b@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: anshuman.khandual@arm.com, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, oupton@kernel.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 17 Mar 2026 02:46:44 +0000, Anshuman Khandual wrote: > > On 13/03/26 3:29 PM, Mark Rutland wrote: > > On Fri, Mar 13, 2026 at 05:38:57AM +0000, Anshuman Khandual wrote: > >> Clear VTCR_EL2 along with VTTBR_EL2 register in __init_el2_stage2(), which > >> ensures that MMU stage-2 translation remain disabled. > > > > As Marc noted, that's not true -- whether stage 2 is enabled is governed > > entirely by HCR_EL2.VM. > > > The only reason to initialize VTCR_EL2 here would be if some field in > > VTCR_EL2 applies when stage 2 is *disabled*. > > Understood. Something similar to VTTBR_EL2.VMID field which > gets into tagged TLB entries for EL0/EL1 translation regime > even when stage-2 is not enabled via HCR_EL2_VM. > > But wondering if VTTBR_EL2.VMID gets cleaned up should not > it also be followed by a "tlbi vmalls12e1 --> dsb --> isb" > sequence to clear existing stale TLB entries ? Why? We already have a TLBI VMALLE1 whenever a CPU boots. That's all we need, and not some random invalidation that serves no purpose as long as S2 is *off*. When we are about to turn S2 on, we have all the required invalidation already. > > > > >> Although clearing out VTTBR_EL2 probably should have been sufficient > >> but adding VTCR_EL2 improves overall safety. > > > > It's unhelpful to send patches like this with unclear or non-existent > > rationale, and vague statements about what the patch might do. Was there > > The commit message could have been more detailed and explicit > about its rationale. Although the intent here was to ensure > improved safety during S2 MMU context initialization. > > > some specific reason to send this? e.g. > > > > * Did you have any specific reason to believe that setting some field in > > VTCR_EL2 was necessary? e.g. is there some misleading documentation, > > or comment elsewhere in the kernel? > > > > * Are you trying to fix some problem you've encountered, but haven't > > managed to debug? > > > > * Was this purely from inspection? > > This was from code inspection while navigating S2 MMU context > initialization and management. I think you should start by improving your understanding of how S2 works *before* sending random patches. Thanks, M. -- Without deviation from the norm, progress is not possible.