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Do we know what translation regimes >> > are affected by the erratum? >> >> Hi Oliver, I got some clarification from the core folks. The issue >> affects the data side of the core only, not the instruction side. I'll >> update my description to include that. >> >> Speculation after the `msr hcr_el2` couldn't launch a problem >> translation when the `msr` is followed by an `isb` like this. > > Thanks, agree that the subsequent ISB protects against speculative > behavior relating to the instruction stream. To be absolutely certain, > there's no risk of, say, a TLB prefetcher pulling in a problematic > translation in this window? IOW, there's no behavior that meets the ARM > ARM definition of a Speculative operation that can lead to a corrupted > translation. Yes, that's right, it's just translations from load/store instructions, and the DSB before closes the window where earlier instructions can get corrupted, and then the ISB after prevents the window for corruption from later instructions from overlapping with the write to HCR. > Sorry to hassle about these issues but they're helpful for maintaining > the workaround in the future. If you can fold all the extra details into > the patch for v2 that'd be great. No worries, and sorry to not have the description more clear originally. I'll include a more complete description in the next version.