From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 357C4CDB483 for ; Wed, 18 Oct 2023 12:43:33 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S230358AbjJRMnd (ORCPT ); Wed, 18 Oct 2023 08:43:33 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34834 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S230305AbjJRMnc (ORCPT ); Wed, 18 Oct 2023 08:43:32 -0400 Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id B97DCA3 for ; Wed, 18 Oct 2023 05:43:30 -0700 (PDT) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 48DC8C433C7; Wed, 18 Oct 2023 12:43:30 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1697633010; bh=t6KGVhsRv9EQvvDPyF01PvPCYq3klVc6018BEpDuOZ8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=uw3rGon9JgKQ3cXXw/3RwixN7hIdCbSg0K6EueSmE9uhZznP2zFMBVhyJkUHapJ0o sucwDynvUVy1xLKwRWv/c56ZwFSleoNYo0YczouQqbI26CROHSL4dIFjUkD7RZ5mh2 pX9wx8iRd6vvEe3izYgsdcab1bsV3/YLFM7ga9dEqCTcfIlvPck9FKjPeluSuUQLkg WECjs+L97m65RpSv2tqFGJU7oRaPRRXy4rlDthYmc+/m6hYEwjkw482Q2dlkowkQf0 cGntFmpSt6qmVC9UiLnBABhrlveGzDNei6VT6SMPwG+8kk0+/gfgWArCSl6r7CABIR lwV6vkA2RlVaA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qt5tX-005LrM-OB; Wed, 18 Oct 2023 13:43:28 +0100 Date: Wed, 18 Oct 2023 13:43:27 +0100 Message-ID: <86pm1cm780.wl-maz@kernel.org> From: Marc Zyngier To: Jeremy Linton Cc: linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org Subject: Re: [PATCH v2 3/3] arm64: cpufeature: Change 32-bit EL0 to display enabled cores In-Reply-To: References: <20231017052322.1211099-1-jeremy.linton@arm.com> <20231017052322.1211099-4-jeremy.linton@arm.com> <86ttqpm8lg.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jeremy.linton@arm.com, linux-arm-kernel@lists.infradead.org, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, anshuman.khandual@arm.com, krisman@suse.de, broonie@kernel.org, james.morse@arm.com, ionela.voinescu@arm.com, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 17 Oct 2023 20:15:43 +0100, Jeremy Linton wrote: > > Hi, > > On 10/17/23 13:01, Marc Zyngier wrote: > > On Tue, 17 Oct 2023 06:23:22 +0100, > > Jeremy Linton wrote: > >> > >> Now that we have the ability to display the list of cores > >> with a feature when it is selectivly enabled, lets display the > >> cores enabled for 32-bit use at EL0. > >> > >> Signed-off-by: Jeremy Linton > >> --- > >> arch/arm64/kernel/cpufeature.c | 15 +++++++++++++-- > >> 1 file changed, 13 insertions(+), 2 deletions(-) > >> > >> diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > >> index b7b67bac0e60..512cbe446b41 100644 > >> --- a/arch/arm64/kernel/cpufeature.c > >> +++ b/arch/arm64/kernel/cpufeature.c > >> @@ -1533,8 +1533,17 @@ static bool has_32bit_el0(const struct arm64_cpu_capabilities *entry, int scope) > >> if (!has_cpuid_feature(entry, scope)) > >> return allow_mismatched_32bit_el0; > >> - if (scope == SCOPE_SYSTEM) > >> - pr_info("detected: 32-bit EL0 Support\n"); > >> + if (scope == SCOPE_SYSTEM) { > >> + struct arm64_cpu_capabilities *has_32bit; > >> + > >> + has_32bit = (struct arm64_cpu_capabilities *)entry; > >> + > >> + has_32bit->cpus = system_32bit_el0_cpumask(); > > > > This seems rather dodgy. 'entry' comes from a static const array which > > will, in all likelihood be mapped R/O pretty soon after the initial > > CPU bringup. Try offlining/onlining a CPU and you should see a > > firework similar to what I have below (I hacked the CnP property, but > > that's no different from what you are doing): > > Yes, dodgy is a good word. The other choices, maintain a mask just for > the print or dump the static key and always use the cpu_32bit_el0_mask > or some combination, weren't much better in the "ick" category. If > anyone sees a better way I'm open to suggestion, although simply > dropping this last patch is fine too. An obvious choice would be to replace the 'cpus' cpumask with a function that evaluates a cpumask stored separately. M. -- Without deviation from the norm, progress is not possible.