From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5B53B12FF7C; Tue, 6 Feb 2024 14:54:16 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707231256; cv=none; b=RtZ2hJ6aB6X1wd6v6uIYn7IAk/62Rr4AORNH1KT3h9Yex5b7t78pO+igkSLKh/L8gkGNodSGZww7TSVlDcLEd4JI2pRgpk+xscpljddM38zzV8OZqZcnVFTcdFilZzbl4w2ii+mhWRnfdvw/mxf6sd2PPKWSMBHbzzrGViWw18w= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1707231256; c=relaxed/simple; bh=FZykc25Fgh62KQdzm9gVnouNp94N7q0i9r9a3bxaxdA=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Qhaw9DMJZiZCNBN+tsa9/gkfVv31zQL9uDf9A58RZmkvqosbTvZ4WY31zg7vcvFb+piwqXvmCM0Zo4wKAjZLe4FfB7NMWd+D3gUFkosd+LBtiR29khIE68Z+HwE+iJmeuIONSqHLOW7MIe4fV7cZh8guVwTWIj5zSCIefApjlnU= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=TOj7ThV4; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="TOj7ThV4" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E799DC433F1; Tue, 6 Feb 2024 14:54:15 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1707231255; bh=FZykc25Fgh62KQdzm9gVnouNp94N7q0i9r9a3bxaxdA=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=TOj7ThV4fk/3L3nP95TbiUIzZXXq/Md4A46Nqfcaf11sbfkRO1CYUYRvvlf07WhaJ vMMxDcdk/yaI0EpwSiWT0Vb0HLeXiEFd1MSTrn28FU3/TpTpxWYTACtOWI8ojUGCuT 6+pugD2r9R+8HKoc+xRTFY+3FGz30hor1Wq9gp3wM2pKQM3eq6NqwZ2T0cHxXwzEPB e8quUcleAeaktBziCfNzYad/NvLs8uHuIffdXEgmjgxxzDIrHF/aVXyJXjJUNptuz1 UIgquNUXAJM2Q6+YZZI4yHtBFxpPvNECUmURepE+MBq8IdY80XWUH/1z6Fh13s/wXP 3GXEIs93OgDIg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1rXMpx-000qjP-L4; Tue, 06 Feb 2024 14:54:13 +0000 Date: Tue, 06 Feb 2024 14:54:12 +0000 Message-ID: <86sf2563u3.wl-maz@kernel.org> From: Marc Zyngier To: "Thierry Reding" Cc: "Jon Hunter" , "Sumit Gupta" , , , , , , , Subject: Re: [Patch] memory: tegra: Skip SID override from Guest VM In-Reply-To: References: <20240206114852.8472-1-sumitg@nvidia.com> <86wmrh6b2n.wl-maz@kernel.org> <252d6094-b2d6-496d-b28f-93507a193ede@nvidia.com> <86v87169g2.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: thierry.reding@gmail.com, jonathanh@nvidia.com, sumitg@nvidia.com, treding@nvidia.com, krzysztof.kozlowski@linaro.org, mark.rutland@arm.com, linux-kernel@vger.kernel.org, linux-tegra@vger.kernel.org, amhetre@nvidia.com, bbasu@nvidia.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 06 Feb 2024 14:07:10 +0000, "Thierry Reding" wrote: > > [1 ] > On Tue Feb 6, 2024 at 1:53 PM CET, Marc Zyngier wrote: > > On Tue, 06 Feb 2024 12:28:27 +0000, Jon Hunter wrote: > > > On 06/02/2024 12:17, Marc Zyngier wrote: > [...] > > > > - My own tegra186 HW doesn't have VHE, since it is ARMv8.0, and this > > > > helper will always return 'false'. How could this result in > > > > something that still works? Can I get a free CPU upgrade? > > > > > > I thought this API just checks to see if we are in EL2? > > > > It does. And that's the problem. On ARMv8.0, we run the Linux kernel > > at EL1. Tegra186 is ARMv8.0 (Denver + A57). So as written, this change > > breaks the very platform it intends to support. > > To clarify, the code that accesses these registers is shared across > Tegra186 and later chips. Tegra194 and later do support ARMv8.1 VHE. But even on these machines that are VHE-capable, not running at EL2 doesn't mean we're running as a guest. The user can force the kernel to stick to EL1, using a command-line option such as kvm-arm.mode=nvhe which will force the kernel to stay at EL1 while deploying KVM at EL2. > Granted, if it always returns false on Tegra186 that's not what we > want. I'm glad we agree here. > > > > - If you assign this device to a VM and that the hypervisor doesn't > > > > correctly virtualise it, then it is a different device and you > > > > should simply advertise it something else. Or even better, fix your > > > > hypervisor. > > > > > > Sumit can add some more details on why we don't completely disable the > > > device for guest OSs. > > > > It's not about disabling it. It is about correctly supporting it > > (providing full emulation for it), or advertising it as something > > different so that SW can handle it differently. > > It's really not a different device. It's exactly the same device except > that accessing some registers isn't permitted. We also can't easily > remove parts of the register region from device tree because these are > intermixed with other registers that we do want access to. But that's the definition of being a different device. It has a different programming interface, hence it is different. The fact that it is the same HW block mediated by a hypervisor doesn't really change that. > > Poking into the internals of how the kernel is booted for a driver > > that isn't tied to the core architecture (because it would need to > > access system registers, for example) is not an acceptable outcome. > > So what would be the better option? Use a different compatible string to > make the driver handle the device differently? Or adding a custom > property to the device tree node to mark this as running in a > virtualized environment? A different compatible string would be my preferred option. An extra property would work as well. As far as I am concerned, these two options are the right way to express the fact that you have something that isn't quite like the real thing. > Perhaps we can reuse the top-level hypervisor node? That seems to only > ever have been used for Xen on 32-bit ARM, so not sure if that'd still > be appropriate. I'd shy away from this. You would be deriving properties from a hypervisor implementation, instead of expressing those properties directly. In my experience, the direct method is always preferable. Thanks, M. -- Without deviation from the norm, progress is not possible.