From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3CF7AC77B75 for ; Wed, 17 May 2023 12:59:31 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231845AbjEQM7a (ORCPT ); Wed, 17 May 2023 08:59:30 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:41008 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S229769AbjEQM72 (ORCPT ); Wed, 17 May 2023 08:59:28 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [139.178.84.217]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 24AC118E for ; Wed, 17 May 2023 05:59:27 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id B5C8563BFE for ; Wed, 17 May 2023 12:59:26 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 245A2C433EF; Wed, 17 May 2023 12:59:26 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684328366; bh=vSsOnzylcUdZ0reW266U97c+33nUMBVRR7mK8LZumhc=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Ce51TIEQPej4IkU6dg8TRQl7RXL9d0HqdWpbpfdKhidP+16O2OvHREDfWEyJdWGue DRvXekGurGg0fx52lHD87xCLCZWUEZtagxG2bm9NxduqM3cfdsLIkH9ubzhZLvnjCS 1D47dmdvAtLVToUGEuft21a1ja2XCEJ+APGLaeQyyHKsEzo19HddOyha9rGmkx2EKO 115p6dIJ844yOPD1qMWPWS4e8OoJG1pfWYb9KUHC6rGzYMTktFT4jOrLSEMZol2+at VSqHMQym3uzw8HCzqxx0DIKa4xOm0fnuCf1GnZ9GhN1PQkLBzK46hjuwMUSB8FXtPw s5jb63Kh2fLqA== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1pzGkV-00FrAE-Tq; Wed, 17 May 2023 13:59:24 +0100 Date: Wed, 17 May 2023 13:59:23 +0100 Message-ID: <86sfbvktas.wl-maz@kernel.org> From: Marc Zyngier To: Yan =?UTF-8?B?WmhlbmfvvIjkuKXmlL/vvIk=?= Cc: "tglx@linutronix.de" , "linux-kernel@vger.kernel.org" , Gao =?UTF-8?B?TWVpdGFv77yI6auY546r5rab77yJ?= , =?UTF-8?B?Ilpob3UgUWlhbyjlkajkvqgpIg==?= , =?UTF-8?B?IlpoYW5nIFpoaXpob3Uo5byg5rK75rSyKSI=?= Subject: Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when reading mpidr In-Reply-To: <9dcef1c9343041c49a92ec8cd40d6331@exch03.asrmicro.com> References: <20230517075500.43516-1-zhengyan@asrmicro.com> <86ttwbl5nq.wl-maz@kernel.org> <9dcef1c9343041c49a92ec8cd40d6331@exch03.asrmicro.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zhengyan@asrmicro.com, tglx@linutronix.de, linux-kernel@vger.kernel.org, meitaogao@asrmicro.com, qiaozhou@asrmicro.com, zhizhouzhang@asrmicro.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Wed, 17 May 2023 11:45:22 +0100, Yan Zheng=EF=BC=88=E4=B8=A5=E6=94=BF=EF=BC=89 wrote: >=20 >=20 >=20 > > -----Original Message----- > > From: Marc Zyngier [mailto:maz@kernel.org] > > Sent: Wednesday, May 17, 2023 4:32 PM > > To: Yan Zheng=EF=BC=88=E4=B8=A5=E6=94=BF=EF=BC=89 > > Cc: tglx@linutronix.de; linux-kernel@vger.kernel.org; Gao Meitao=EF=BC= =88=E9=AB=98=E7=8E=AB=E6=B6=9B=EF=BC=89 > > ; Zhou Qiao(=E5=91=A8=E4=BE=A8) ; > > Zhang Zhizhou(=E5=BC=A0=E6=B2=BB=E6=B4=B2) > > Subject: Re: [PATCH] irqchip/gic-v3: workaround for ASR8601 when reading > > mpidr > >=20 > > On Wed, 17 May 2023 08:55:00 +0100, > > zhengyan wrote: > > > > > > This patch add workaround for ASR8601, which uses an armv8.2 processor > > > with a gic-500. ARMv8.2 uses Multiprocessor Affinity Register to > > > identify the logical address of the core by > > > | cluster | core | thread |. > >=20 > > Not quite. The ARMv8.2 architecture doesn't say *any* of that. It is AR= M's > > *implementations* that follow this scheme. > >=20 >=20 > Really thank you for rapid response,=20 > Yes, as arm documents > https://developer.arm.com/docuentation/ka002107/latest said This page doesn't exist. > It comes from armv8.2 get 3 types for affinity (arm v8.0 cpus only get 2 = types) > And it's an implementations issue. Again, this has nothing to do with the ARMv8.2 architecture. Nor the ARMv8.0 architecture. Please read the ARM ARM, which says absolutely *nothing* of what the various affinity levels are for. >=20 > > > However, gic-500 only supports topologies with affinity levels less > > > than 2 as > > > | cluster | core|. > > > > > > So it needs this patch to shift the MPIDR values to ensure proper > > > functionality > > > > > > Signed-off-by: zhengyan > > > --- > > > drivers/irqchip/irq-gic-v3.c | 28 +++++++++++++++++++++++++++- > > > 1 file changed, 27 insertions(+), 1 deletion(-) > > > > > > diff --git a/drivers/irqchip/irq-gic-v3.c > > > b/drivers/irqchip/irq-gic-v3.c index 6fcee221f201..435b98a8641e 100644 > > > --- a/drivers/irqchip/irq-gic-v3.c > > > +++ b/drivers/irqchip/irq-gic-v3.c > > > @@ -39,6 +39,7 @@ > > > > > > #define FLAGS_WORKAROUND_GICR_WAKER_MSM8996 (1ULL << 0) > > > #define FLAGS_WORKAROUND_CAVIUM_ERRATUM_38539 (1ULL << 1) > > > +#define FLAGS_WORKAROUND_MPIDR_ASR8601 (1ULL << 2) > >=20 > > What is ASR8601? Is it a system? Or an erratum number? For issues that = are the > > result of a HW integration issue, please provide an official erratum nu= mber, and > > update Documentation/arm64/silicon-errata.rst. > >=20 >=20 > ASR8601 is our soc's name, and yes it=E2=80=99s a kind of HW integration = issue > But maybe it=E2=80=99s not an erratum since our HW design is like that, a= lthough > Arm doesn't recommend this way. Yes, for a good reason: it doesn't work. So this is *definitely* an erratum, no ifs, no buts. > And I would like to add more comments > Under the next part before *desc =3D "GICv3: ASR 8601 MPIDR shift"* > Maybe this is a better way? Or add something under Documentation=EF=BC=9F Documentation/arm64/silicon-errata.rst is the place to put it. Nowhere else. M. --=20 Without deviation from the norm, progress is not possible.