From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6211A356A1A; Mon, 12 Jan 2026 11:20:10 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768216810; cv=none; b=KexzbLM8eU6tkhOkgxWbqlBB7fSVtcL2imF9DoglF59iSx1AIzbR0MoyC1illXuIaVAqSV/dAQT0vioxZanucLh2/cMQjHWCO21ntcqGwWqMgdXnZAjXhRovjXckPQTCl2dMD7DX32q5xcyMh4U9ur3lSAquzoMYa8YZA3p/VZs= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1768216810; c=relaxed/simple; bh=cJwAJiB1jDAkBYN22k41gWvMxKzsKOodAtpaC8n3zfk=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=fOOz/ACuh1sSwLoHp4QSxnhJTiWH/pPPx9Gm+It/e2C4PwgyaL5BVKasG1JDCSOrmC9zAu0hOcGwiA8si7SyUxC19cKX93w0YjPtfSmQnMwHspjvo0WJFARUNdQBBYDpwCNZ34Kyt6nTiaTJtiOTrl9SK1InaBJptE6wjolWDfo= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=k+YTDjvL; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="k+YTDjvL" Received: by smtp.kernel.org (Postfix) with ESMTPSA id E8815C19425; Mon, 12 Jan 2026 11:20:09 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1768216810; bh=cJwAJiB1jDAkBYN22k41gWvMxKzsKOodAtpaC8n3zfk=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=k+YTDjvLgj0Ngt3Asj6+TNfDI47XpsY5fG5ZrR5Eq1cVmMxduFr8OOyQs40ioUa8l HHQxofOYUHuj6/fWBq01ZDoN0P3VbXRL5NYWnHaoPnwEVTm5kJZH2MoIR6i4djptmC 4i+Ps2suLKI2ayaLNbcDQjjlvqb+8zqrYQmFchh04HxV0KdnBoC7rZ5sPsqHzbRAC8 V2k3JyIA9RSjJYoisal5jgUC2EKlulBnzyNqV22OEq/PG3HKyuwEW6+jlscVbYdh9v X5aus6OFAMiojLxDSja2Z3houjEUZ6RSl2I/q2J7YKtg5S/seUF/7IxBNjmlnQRTeT EmBhiEBOERY1A== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1vfFxv-00000001PSo-2ND2; Mon, 12 Jan 2026 11:20:07 +0000 Date: Mon, 12 Jan 2026 11:20:07 +0000 Message-ID: <86tswrkrh4.wl-maz@kernel.org> From: Marc Zyngier To: Waiman Long , Thomas Gleixner Cc: Sebastian Andrzej Siewior , Clark Williams , Steven Rostedt , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rt-devel@lists.linux.dev Subject: Re: [PATCH] irqchip/gic-v3-its: Don't acquire rt_spin_lock in allocate_vpe_l1_table() In-Reply-To: <87pl7gglya.ffs@tglx> References: <20260107215353.75612-1-longman@redhat.com> <864iowmrx6.wl-maz@kernel.org> <87ms2nsqju.ffs@tglx> <86wm1qlq7l.wl-maz@kernel.org> <87ecnwij44.ffs@tglx> <86v7h8l9ht.wl-maz@kernel.org> <87pl7gglya.ffs@tglx> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: longman@redhat.com, tglx@kernel.org, bigeasy@linutronix.de, clrkwllms@kernel.org, rostedt@goodmis.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-rt-devel@lists.linux.dev X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sun, 11 Jan 2026 16:20:45 +0000, Thomas Gleixner wrote: > > On Sun, Jan 11 2026 at 10:38, Marc Zyngier wrote: > > On Sun, 11 Jan 2026 09:39:07 +0000, > > Thomas Gleixner wrote: > >> > >> On Fri, Jan 09 2026 at 16:13, Marc Zyngier wrote: > >> > On Thu, 08 Jan 2026 22:11:33 +0000, > >> > Thomas Gleixner wrote: > >> >> At the point where a CPU is brought up, the topology should be known > >> >> already, which means this can be allocated on the control CPU _before_ > >> >> the new CPU comes up, no? > >> > > >> > No. Each CPU finds *itself* in the forest of redistributors, and from > >> > there tries to find whether it has some shared resource with a CPU > >> > that has booted before it. That's because firmware is absolutely awful > >> > and can't present a consistent view of the system. > >> > >> Groan.... > >> > >> > Anyway, I expect it could be solved by moving this part of the init to > >> > an ONLINE HP callback. > >> > >> Which needs to be before CPUHP_AP_IRQ_AFFINITY_ONLINE, but even that > >> might be to late because there are callbacks in the STARTING section, > >> i.e. timer, perf, which might rely on interrupts being accessible. > > > > Nah. This stuff is only for direct injection of vLPIs into guests, so > > as long as this is done before we can schedule a vcpu on this physical > > CPU, we're good. No physical interrupt is concerned with this code. > > That's fine then. vCPUs are considered "user-space" tasks and can't be > scheduled before CPUHP_AP_ACTIVE sets the CPU active for the scheduler. Waiman, can you please give the following hack a go on your box? The machines I have are thankfully limited to a single ITS group, so I can't directly reproduce your issue. Thanks, M. diff --git a/drivers/irqchip/irq-gic-v3-its.c b/drivers/irqchip/irq-gic-v3-its.c index ada585bfa4517..20967000f2348 100644 --- a/drivers/irqchip/irq-gic-v3-its.c +++ b/drivers/irqchip/irq-gic-v3-its.c @@ -2896,7 +2896,7 @@ static bool allocate_vpe_l2_table(int cpu, u32 id) return true; } -static int allocate_vpe_l1_table(void) +static int allocate_vpe_l1_table(unsigned int cpu) { void __iomem *vlpi_base = gic_data_rdist_vlpi_base(); u64 val, gpsz, npg, pa; @@ -3012,10 +3012,11 @@ static int allocate_vpe_l1_table(void) out: gicr_write_vpropbaser(val, vlpi_base + GICR_VPROPBASER); - cpumask_set_cpu(smp_processor_id(), gic_data_rdist()->vpe_table_mask); + cpumask_set_cpu(cpu, gic_data_rdist()->vpe_table_mask); + dsb(sy); pr_debug("CPU%d: VPROPBASER = %llx %*pbl\n", - smp_processor_id(), val, + cpu, val, cpumask_pr_args(gic_data_rdist()->vpe_table_mask)); return 0; @@ -3264,15 +3265,9 @@ static void its_cpu_init_lpis(void) val = its_clear_vpend_valid(vlpi_base, 0, 0); } - if (allocate_vpe_l1_table()) { - /* - * If the allocation has failed, we're in massive trouble. - * Disable direct injection, and pray that no VM was - * already running... - */ - gic_rdists->has_rvpeid = false; - gic_rdists->has_vlpis = false; - } + if (smp_processor_id() == 0) + cpuhp_setup_state(CPUHP_AP_ONLINE_DYN, "irqchip/arm/gicv3:vpe", + allocate_vpe_l1_table, NULL); /* Make sure the GIC has seen the above */ dsb(sy); -- Without deviation from the norm, progress is not possible.