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Mon, 11 Aug 2025 15:54:15 +0100 Date: Mon, 11 Aug 2025 15:54:14 +0100 Message-ID: <86tt2d9aeh.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, Jinjie Ruan , Thomas Gleixner Subject: Re: [PATCH] irqchip/gic-v5: Fix kmemleak L2 IST table entries false positives In-Reply-To: <20250811135001.1333684-1-lpieralisi@kernel.org> References: <20250811135001.1333684-1-lpieralisi@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, ruanjinjie@huawei.com, tglx@linutronix.de X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 11 Aug 2025 14:50:01 +0100, Lorenzo Pieralisi wrote: > > L2 IST table entries are allocated with the kmalloc interface > and their physical addresses are programmed in the GIC (either > IST base address register or L1 IST table entries) but their > virtual addresses are not stored in any kernel data structure > because they are not needed at runtime - the L2 IST table entries > are managed through system instructions but never dereferenced > directly by the driver. > > This triggers kmemleak false positive reports: > > unreferenced object 0xffff00080039a000 (size 4096): > comm "swapper/0", pid 0, jiffies 4294892296 > hex dump (first 32 bytes): > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 ................ > backtrace (crc 0): > kmemleak_alloc+0x34/0x40 > __kmalloc_noprof+0x320/0x464 > gicv5_irs_iste_alloc+0x1a4/0x484 > gicv5_irq_lpi_domain_alloc+0xe4/0x194 > irq_domain_alloc_irqs_parent+0x78/0xd8 > gicv5_irq_ipi_domain_alloc+0x180/0x238 > irq_domain_alloc_irqs_locked+0x238/0x7d4 > __irq_domain_alloc_irqs+0x88/0x114 > gicv5_of_init+0x284/0x37c > of_irq_init+0x3b8/0xb18 > irqchip_init+0x18/0x40 > init_IRQ+0x104/0x164 > start_kernel+0x1a4/0x3d4 > __primary_switched+0x8c/0x94 > > Instruct kmemleak to ignore L2 IST table memory allocation > virtual addresses to prevent these false positive reports. > > Reported-by: Jinjie Ruan > Closes: https://lore.kernel.org/lkml/cc611dda-d1e4-4793-9bb2-0eaa47277584@huawei.com/ > Signed-off-by: Lorenzo Pieralisi > Cc: Thomas Gleixner > Cc: Marc Zyngier > --- > drivers/irqchip/irq-gic-v5-irs.c | 3 +++ > 1 file changed, 3 insertions(+) > > diff --git a/drivers/irqchip/irq-gic-v5-irs.c b/drivers/irqchip/irq-gic-v5-irs.c > index ad1435a858a4..e8a576f66366 100644 > --- a/drivers/irqchip/irq-gic-v5-irs.c > +++ b/drivers/irqchip/irq-gic-v5-irs.c > @@ -5,6 +5,7 @@ > > #define pr_fmt(fmt) "GICv5 IRS: " fmt > > +#include > #include > #include > #include > @@ -117,6 +118,7 @@ static int __init gicv5_irs_init_ist_linear(struct gicv5_irs_chip_data *irs_data > kfree(ist); > return ret; > } > + kmemleak_ignore(ist); > > return 0; > } > @@ -232,6 +234,7 @@ int gicv5_irs_iste_alloc(const u32 lpi) > kfree(l2ist); > return ret; > } > + kmemleak_ignore(l2ist); > > /* > * Make sure we invalidate the cache line pulled before the IRS Acked-by: Marc Zyngier M. -- Without deviation from the norm, progress is not possible.