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From: Marc Zyngier <maz@kernel.org>
To: Lorenzo Pieralisi <lpieralisi@kernel.org>
Cc: Thomas Gleixner <tglx@linutronix.de>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Catalin Marinas <catalin.marinas@arm.com>,
	Will Deacon <will@kernel.org>, Arnd Bergmann <arnd@arndb.de>,
	Sascha Bischoff <sascha.bischoff@arm.com>,
	Timothy Hayes <timothy.hayes@arm.com>,
	"Liam R. Howlett" <Liam.Howlett@oracle.com>,
	Mark Rutland <mark.rutland@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	linux-kernel@vger.kernel.org, devicetree@vger.kernel.org
Subject: Re: [PATCH v2 21/22] irqchip/gic-v5: Add GICv5 IWB support
Date: Thu, 01 May 2025 15:15:46 +0100	[thread overview]
Message-ID: <86tt64h0x9.wl-maz@kernel.org> (raw)
In-Reply-To: <aBJO9GEyb+0t6W6u@lpieralisi>

On Wed, 30 Apr 2025 17:25:24 +0100,
Lorenzo Pieralisi <lpieralisi@kernel.org> wrote:
> 
> I wrote a diff against the heavily reworked series in progress I have,
> (so it does not apply on v2 - headers moved) with what I came up with
> for the IWB MBIgen like. It works - it removes lots of boilerplate code
> but there is a hack we never really liked in:
> 
> gicv5_its_msi_prepare()
> 
> that is, using the OF compatible string to detect if we are an IWB or not.

You shouldn't need that. The MSI_FLAG_USE_DEV_FWNODE should be a good
enough indication that this is something of interest, and that ends-up
in the .init_dev_msi_info() callback.

> If we are, we use the msi_alloc_info_t->hwirq to define the LPI eventid,
> basically the IWB wire, if not we just allocate an eventid available from
> the device bitmap.
> 
> Other than that (and being forced to provide an IWB irqchip.irq_write_msi_msg()
> pointer even if the IWB can't write anything otherwise we dereference
> NULL) this works.

Not even MBIGEN allows you to change the event. If you really want to
ensure things are even tighter, invent a MSI_FLAG_HARDCODED_MSG flag,
and pass that down the prepare path.

> Is there a better way to implement this ? I would post this code with
> v3 but instead of waiting I thought I could inline it here, feel free
> to ignore it (or flame me if it is a solved problem I failed to spot,
> we need to find a way for the IWB driver to pass the "fixed event" info
> to the ITS - IWB eventIDs are hardwired it is not like the MBIgen where
> the irq_write_msi_msg() callback programs the wire-to-eventid
> translation in HW).

It's *exactly* the same. And see above for a potential explicit
solution. The empty irq_write_msi_msg() is not a problem. It's
actually pretty clean, given how the whole thing works.

Please fold this into your v3, and we'll take it from there.

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2025-05-01 14:15 UTC|newest]

Thread overview: 43+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-04-24 10:25 [PATCH v2 00/22] Arm GICv5: Host driver implementation Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 01/22] dt-bindings: interrupt-controller: Add Arm GICv5 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 02/22] arm64/sysreg: Add GCIE field to ID_AA64PFR2_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 03/22] arm64/sysreg: Add ICC_PPI_PRIORITY<n>_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 04/22] arm64/sysreg: Add ICC_ICSR_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 05/22] arm64/sysreg: Add ICC_PPI_HMR<n>_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 06/22] arm64/sysreg: Add ICC_PPI_ENABLER<n>_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 07/22] arm64/sysreg: Add ICC_PPI_{C/S}ACTIVER<n>_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 08/22] arm64/sysreg: Add ICC_PPI_{C/S}PENDR<n>_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 09/22] arm64/sysreg: Add ICC_CR0_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 10/22] arm64/sysreg: Add ICC_PCR_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 11/22] arm64/sysreg: Add ICC_IDR0_EL1 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 12/22] arm64/sysreg: Add ICH_HFGRTR_EL2 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 13/22] arm64/sysreg: Add ICH_HFGWTR_EL2 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 14/22] arm64/sysreg: Add ICH_HFGITR_EL2 Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 15/22] arm64: Disable GICv5 read/write/instruction traps Lorenzo Pieralisi
2025-05-01 14:32   ` Marc Zyngier
2025-04-24 10:25 ` [PATCH v2 16/22] arm64: cpucaps: Rename GICv3 CPU interface capability Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 17/22] arm64: cpucaps: Add GICv5 CPU interface (GCIE) capability Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 18/22] arm64: smp: Support non-SGIs for IPIs Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 19/22] irqchip/gic-v5: Add GICv5 CPU interface/IRS support Lorenzo Pieralisi
2025-04-28 15:49   ` Marc Zyngier
2025-04-29 14:54     ` Lorenzo Pieralisi
2025-04-29 15:38       ` Marc Zyngier
2025-04-29 16:02         ` Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 20/22] irqchip/gic-v5: Add GICv5 ITS support Lorenzo Pieralisi
2025-04-30  7:28   ` Jiri Slaby
2025-04-30 12:55     ` Lorenzo Pieralisi
2025-04-30  9:12   ` Marc Zyngier
2025-04-30 13:21     ` Lorenzo Pieralisi
2025-05-01  9:01       ` Marc Zyngier
2025-04-24 10:25 ` [PATCH v2 21/22] irqchip/gic-v5: Add GICv5 IWB support Lorenzo Pieralisi
2025-04-30 11:57   ` Marc Zyngier
2025-04-30 13:27     ` Lorenzo Pieralisi
2025-05-01 13:27       ` Marc Zyngier
2025-05-02  7:59         ` Lorenzo Pieralisi
2025-05-02 14:50           ` Marc Zyngier
2025-05-02 15:43           ` Marc Zyngier
2025-05-02 16:16             ` Lorenzo Pieralisi
2025-04-30 16:25     ` Lorenzo Pieralisi
2025-05-01 14:15       ` Marc Zyngier [this message]
2025-05-02  8:04         ` Lorenzo Pieralisi
2025-04-24 10:25 ` [PATCH v2 22/22] arm64: Kconfig: Enable GICv5 Lorenzo Pieralisi

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