From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5039213C9C2 for ; Wed, 10 Apr 2024 08:50:22 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712739023; cv=none; b=N+AhSDnnkjUEeWmH3lMY3TczuDxcMfYUZqfkYiQlMrbo/u3IZgy6xDQouIo2SW0axF7t9iU4tG4sppLwoTlGvxPcQTHqYt3Fgh9rdPc+cIqCFnINIqOcZzBHXyTddryNBMm6s0PyPezk68oFS2ydExE2ac2oRByB+zTNXqJtJ8s= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1712739023; c=relaxed/simple; bh=mREyrzvoUM7UuFGn1kCnxfo+7q349N2icGn7lRUNV+g=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=esqIUDQTvJ/ViXHbqDDj2O0Xi28BS/xtqJ3k6guMqbu/UpZ4tRQBNbW/nGJtfmcudNcBVH3El+PJnJ08+nW7pdLSe0XeWAIEOGHImk6r3Zelaf5nzvlWOmdBoJvPbx07WTfVsbX8KW5+nHE0MHtH2UpMYXwg/LkjoqcqCAvmeLg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=C7AtuZ+a; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="C7AtuZ+a" Received: by smtp.kernel.org (Postfix) with ESMTPSA id C9FE6C433F1; Wed, 10 Apr 2024 08:50:22 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1712739022; bh=mREyrzvoUM7UuFGn1kCnxfo+7q349N2icGn7lRUNV+g=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=C7AtuZ+aFExyX1OzrWiO3avS8l8UAzvvnXOIpHSGp5wGrQsTag/FUrTxMcgnuo6l6 fFuLNZe8zteJevwbS1jBge9ft0g/GSzpCdXyruYVTBqLr1J59DFZ1vsGgntNYIeQf0 u7blDHT7QDvbnsY+figC8UgIm678hMgH5DqteA8G8o2TsWNldtdjJiVysR0ajm0WNO njeygczxlR14neXcplmhq/vl0JMaLr2aO7rMEwst16L8HDrZ3vm/CrCWHebZO1LeVF 44gFNrKf3aOguMSUsCqgIuUlmmkYsIkdfmClX1DP80FtyMdRZmPwunYorZilvFN5Kk 8dL8DVUzfdDsQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1ruTeu-0034xO-ET; Wed, 10 Apr 2024 09:50:20 +0100 Date: Wed, 10 Apr 2024 09:50:20 +0100 Message-ID: <86v84psisz.wl-maz@kernel.org> From: Marc Zyngier To: Ryan Roberts Cc: Gavin Shan , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, oliver.upton@linux.dev, apopple@nvidia.com, rananta@google.com, mark.rutland@arm.com, v-songbaohua@oppo.com, yangyicong@hisilicon.com, shahuang@redhat.com, yihyu@redhat.com, shan.gavin@gmail.com Subject: Re: [PATCH v3 3/3] arm64: tlb: Allow range operation for MAX_TLBI_RANGE_PAGES In-Reply-To: <27718d41-32cb-4976-b50e-e9237da7aedf@arm.com> References: <20240405035852.1532010-1-gshan@redhat.com> <20240405035852.1532010-4-gshan@redhat.com> <27718d41-32cb-4976-b50e-e9237da7aedf@arm.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: ryan.roberts@arm.com, gshan@redhat.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, catalin.marinas@arm.com, will@kernel.org, akpm@linux-foundation.org, oliver.upton@linux.dev, apopple@nvidia.com, rananta@google.com, mark.rutland@arm.com, v-songbaohua@oppo.com, yangyicong@hisilicon.com, shahuang@redhat.com, yihyu@redhat.com, shan.gavin@gmail.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Mon, 08 Apr 2024 09:43:44 +0100, Ryan Roberts wrote: > > On 05/04/2024 04:58, Gavin Shan wrote: > > MAX_TLBI_RANGE_PAGES pages is covered by SCALE#3 and NUM#31 and it's > > supported now. Allow TLBI RANGE operation when the number of pages is > > equal to MAX_TLBI_RANGE_PAGES in __flush_tlb_range_nosync(). > > > > Suggested-by: Marc Zyngier > > Signed-off-by: Gavin Shan > > Reviewed-by: Ryan Roberts > > > --- > > arch/arm64/include/asm/tlbflush.h | 4 ++-- > > 1 file changed, 2 insertions(+), 2 deletions(-) > > > > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > > index 243d71f7bc1f..95fbc8c05607 100644 > > --- a/arch/arm64/include/asm/tlbflush.h > > +++ b/arch/arm64/include/asm/tlbflush.h > > @@ -446,11 +446,11 @@ static inline void __flush_tlb_range_nosync(struct vm_area_struct *vma, > > * When not uses TLB range ops, we can handle up to > > * (MAX_DVM_OPS - 1) pages; > > * When uses TLB range ops, we can handle up to > > - * (MAX_TLBI_RANGE_PAGES - 1) pages. > > + * MAX_TLBI_RANGE_PAGES pages. > > */ > > if ((!system_supports_tlb_range() && > > (end - start) >= (MAX_DVM_OPS * stride)) || > > - pages >= MAX_TLBI_RANGE_PAGES) { > > + pages > MAX_TLBI_RANGE_PAGES) { > > As a further enhancement, I wonder if it might be better to test: > > pages * 4 / MAX_TLBI_RANGE_PAGES > MAX_DVM_OPS > > Then add an extra loop over __flush_tlb_range_op(), like KVM does. > > The math is trying to express that there are a maximum of 4 tlbi range > instructions for MAX_TLBI_RANGE_PAGES pages (1 per scale) and we only need to > fall back to flushing the whole mm if it could generate more than MAX_DVM_OPS ops. That'd be a good enhancement indeed, although I wonder if that occurs as often as we see it on the KVM side. But in any case, adding consistency amongst the users of __flush_tlb_range_op() can only be beneficial. Thanks, M. -- Without deviation from the norm, progress is not possible.