From: Marc Zyngier <marc.zyngier@arm.com>
To: Stafford Horne <shorne@gmail.com>
Cc: LKML <linux-kernel@vger.kernel.org>,
Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>,
Thomas Gleixner <tglx@linutronix.de>,
Jason Cooper <jason@lakedaemon.net>,
Rob Herring <robh+dt@kernel.org>,
Mark Rutland <mark.rutland@arm.com>,
Jonas Bonn <jonas@southpole.se>,
"David S. Miller" <davem@davemloft.net>,
Greg Kroah-Hartman <gregkh@linuxfoundation.org>,
Mauro Carvalho Chehab <mchehab@kernel.org>,
Randy Dunlap <rdunlap@infradead.org>,
devicetree@vger.kernel.org, openrisc@lists.librecores.org
Subject: Re: [PATCH v4 05/13] irqchip: add initial support for ompic
Date: Mon, 30 Oct 2017 06:11:40 +0000 [thread overview]
Message-ID: <86vaix5fmr.fsf@arm.com> (raw)
In-Reply-To: <20171030041806.GA29237@lianli.shorne-pla.net> (Stafford Horne's message of "Mon, 30 Oct 2017 13:18:06 +0900")
On Mon, Oct 30 2017 at 1:18:06 pm GMT, Stafford Horne <shorne@gmail.com> wrote:
> On Mon, Oct 30, 2017 at 02:29:18AM +0000, Marc Zyngier wrote:
>> On Mon, Oct 30 2017 at 8:11:15 am GMT, Stafford Horne <shorne@gmail.com> wrote:
>> > From: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>> >
>> > IPI driver for the Open Multi-Processor Interrupt Controller (ompic) as
>> > described in the Multi-core support section of the OpenRISC 1.2
>> > architecture specification:
>> >
>> > https://github.com/openrisc/doc/raw/master/openrisc-arch-1.2-rev0.pdf
>> >
>> > Each OpenRISC core contains a full interrupt controller which is used in
>> > the SMP architecture for interrupt balancing. This IPI device, the
>> > ompic, is the only external device required for enabling SMP on
>> > OpenRISC.
>> >
>> > Pending ops are stored in a memory bit mask which can allow multiple
>> > pending operations to be set and serviced at a time. This is mostly
>> > borrowed from the alpha IPI implementation.
>> >
>> > Cc: Marc Zyngier <marc.zyngier@arm.com>
>> > Acked-by: Rob Herring <robh@kernel.org>
>> > Signed-off-by: Stefan Kristiansson <stefan.kristiansson@saunalahti.fi>
>> > [shorne@gmail.com: converted ops to bitmask, wrote commit message]
>> > Signed-off-by: Stafford Horne <shorne@gmail.com>
>>
>> Reviewed-by: Marc Zyngier <marc.zyngier@arm.com>
>
> Thanks
>
>> Side question: what is your merge strategy for this? I can take it
>> through the irqchip tree as it is standalone, but I'm open to other
>> suggestions.
>
> For me its easier if I just take it through the openrisc tree, as
> there are dependencies between this series and the irqchip driver.
> If you are ok with that I can make a note to Linus indicating so in
> the pull request.
No problem, that's OK with me.
> My plan is to send this series during the 4.15 merge window.
Make sure this is in -next (when it comes back to life...).
Thanks,
M.
--
Jazz is not dead. It just smells funny.
next prev parent reply other threads:[~2017-10-30 6:11 UTC|newest]
Thread overview: 23+ messages / expand[flat|nested] mbox.gz Atom feed top
2017-10-29 23:11 [PATCH v4 00/13] OpenRISC SMP Support Stafford Horne
2017-10-29 23:11 ` [PATCH v4 01/13] openrisc: use shadow registers to save regs on exception Stafford Horne
2017-10-29 23:11 ` [PATCH v4 02/13] openrisc: add 1 and 2 byte cmpxchg support Stafford Horne
2017-10-29 23:11 ` [PATCH v4 03/13] openrisc: use qspinlocks and qrwlocks Stafford Horne
2017-10-29 23:11 ` [PATCH v4 04/13] dt-bindings: add openrisc to vendor prefixes list Stafford Horne
2017-10-29 23:11 ` [PATCH v4 05/13] irqchip: add initial support for ompic Stafford Horne
2017-10-30 2:29 ` Marc Zyngier
2017-10-30 4:18 ` Stafford Horne
2017-10-30 6:11 ` Marc Zyngier [this message]
2017-11-01 12:17 ` Stafford Horne
2017-10-29 23:11 ` [PATCH v4 06/13] openrisc: initial SMP support Stafford Horne
2017-10-29 23:11 ` [PATCH v4 07/13] openrisc: fix initial preempt state for secondary cpu tasks Stafford Horne
2017-10-29 23:11 ` [PATCH v4 08/13] openrisc: sleep instead of spin on secondary wait Stafford Horne
2017-10-29 23:11 ` [PATCH v4 09/13] openrisc: add cacheflush support to fix icache aliasing Stafford Horne
2017-10-29 23:11 ` [PATCH v4 10/13] openrisc: add simple_smp dts and defconfig for simulators Stafford Horne
2017-10-29 23:11 ` [PATCH v4 11/13] openrisc: support framepointers and STACKTRACE_SUPPORT Stafford Horne
2017-10-29 23:11 ` [PATCH v4 12/13] openrisc: enable LOCKDEP_SUPPORT and irqflags tracing Stafford Horne
2017-10-29 23:11 ` [PATCH v4 13/13] openrisc: add tick timer multi-core sync logic Stafford Horne
2017-10-31 14:06 ` Matt Redfearn
2017-10-31 23:17 ` Stafford Horne
2017-11-01 0:34 ` Stafford Horne
2017-11-01 9:26 ` Matt Redfearn
2017-11-01 12:15 ` Stafford Horne
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