From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 6923418641; Mon, 12 May 2025 08:32:54 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747038776; cv=none; b=HzWg1qfZoqUQwAFEAgKa1uO/Qm/KUBTeWG9L2lWxxMMbezmrSzBhNHAIZlfNZPShLrWRg7dsFSl8ihVyHmfpizRUqR6cEy/LHdSa8NA6fxiAl5g+4k+AqScvVg7uDwmWmf0lTIrFItNJcsLnEc5fpSMRgnJScN06JL6VnaatKkQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1747038776; c=relaxed/simple; bh=3E+9roOzG0uDBJJlhQpnjD/rLvYcI1x7SJ02lswokIY=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Fy5cv5Ojc1K/5dZviJvhC78MiWBUFrAMKFUXIbHf523S7vELf85sVOlxXw3ukKqOnfNryie/eRW4+An20wNNcELTWBWsFwhPgpwa8qJGq9XySHM7RcGIXnW5peG4PhwUT7q/CxkBATcp6Kl0J/bWmTP9XduYIdBRVdekbIS0YjM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=F/Z06Vmf; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="F/Z06Vmf" Received: by smtp.kernel.org (Postfix) with ESMTPSA id A8B78C4CEE7; Mon, 12 May 2025 08:32:54 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1747038774; bh=3E+9roOzG0uDBJJlhQpnjD/rLvYcI1x7SJ02lswokIY=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=F/Z06Vmf14lo5BA+l5yANEOuRLz+FeA5JPYog63df1VgYCivcLb+baKzjUZ4QRqBA +Ud++cIOyR+Og5tQgXbIhS1uJiJwDn34aSWPEjqLgJLzE9/5T2ljeMN1PP1VTK2JCy SZqlxO6BNBKEM6wzzJVBzFXSh/hnETtHJXFQofhYXdaLSt4VdH3XWtefBlnI3HWTHu Hi1akeCIT48l6ZjxppvpgsmOryuZ2hHeP7Bd5vbRRl28egnS2ViXsOzbSHa9AZ27sS kr0IWWgck8eoIlvJH8K1qWrLmvjQRTbFkIpH0yVQgW+8xpLp12o9DAPTaZmiRYwFVD /0k1wOSIzrm/Q== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1uEOai-00E2lX-HX; Mon, 12 May 2025 09:32:52 +0100 Date: Mon, 12 May 2025 09:32:52 +0100 Message-ID: <86wmamfcuj.wl-maz@kernel.org> From: Marc Zyngier To: Lorenzo Pieralisi Cc: Thomas Gleixner , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Catalin Marinas , Will Deacon , Arnd Bergmann , Sascha Bischoff , Timothy Hayes , "Liam R. Howlett" , Mark Rutland , Jiri Slaby , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org Subject: Re: [PATCH v3 20/25] irqchip/gic-v5: Add GICv5 PPI support In-Reply-To: References: <20250506-gicv5-host-v3-20-6edd5a92fd09@kernel.org> <87zffpn5rk.ffs@tglx> <86a57ohjey.wl-maz@kernel.org> <87ecx0mt9p.ffs@tglx> <867c2sh6jx.wl-maz@kernel.org> <874ixwmpto.ffs@tglx> <864ixvh4ss.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: lpieralisi@kernel.org, tglx@linutronix.de, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, catalin.marinas@arm.com, will@kernel.org, arnd@arndb.de, sascha.bischoff@arm.com, timothy.hayes@arm.com, Liam.Howlett@oracle.com, mark.rutland@arm.com, jirislaby@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Fri, 09 May 2025 09:35:25 +0100, Lorenzo Pieralisi wrote: > > On Fri, May 09, 2025 at 10:07:44AM +0200, Lorenzo Pieralisi wrote: > > On Thu, May 08, 2025 at 12:44:45PM +0200, Lorenzo Pieralisi wrote: > > > > [...] > > > > > I noticed that, if the irq_set_type() function is not implemented, > > > we don't execute (in __irq_set_trigger()): > > > > > > irq_settings_set_level(desc); > > > irqd_set(&desc->irq_data, IRQD_LEVEL); > > > > I don't get why the settings above are written only if the irqchip > > has an irq_set_type() method, maybe they should be updated in > > irqdomain code (?) where: > > > > irqd_set_trigger_type() > > > > is executed after creating the fwspec mapping ? > > > > Is it possible we never noticed because we have always had irqchips that > > do implement irq_set_type() ? > > > > Again, I don't know the history behind the IRQD_LEVEL flag so it is just > > a question, I'd need to get this clarified though please if I remove the > > PPI irq_set_type() callback. > > https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/arch/powerpc/platforms/52xx/mpc52xx_pic.c?h=v6.15-rc5#n218 > > There are other examples in powerpc, this does not look right to me. I don't see what's wrong with this, given that PPC is about 15 years behind the curve when it comes to interrupt management. Better than Sparc or Alpha, though. So they do whatever was possible at the time this code was written. It doesn't mean that you need to align with the worse we have in the tree! M. -- Without deviation from the norm, progress is not possible.