From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id CAD2A15198D for ; Wed, 5 Feb 2025 14:14:34 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738764874; cv=none; b=B2gU/4+0+VV7V3KtVVqz77MWeZVVrKQsHnOUTSA0b++3YdzDe/DZUa29qVA6EIE5eO87XHoBM080q9wzslfscDgoI6zMr6bbQ11h0iMej9dOpgmP3lUeosT05EMqQ8vjLrj3+d4p3Se9y7z8q0tRrZ01vXGJqvf+KmHB+1PhreU= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1738764874; c=relaxed/simple; bh=FidpCX5GxjvcT+vVJZsxzD/fUKwHxS5XyiCZNAkvy+A=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=SmkwyZ/EukLnX4eAEIpG9rRbZL7nBzLMB+w5hrKtlVQ2k/ex23eKaz968BYcASCuNHNtuD1D9iMciiQmHYJ1H0y8In4Vfa12h8c1GXDG6X0XBkp7C51rpCXb0byHhQ4Aii9BcOGa61iCqYaTtbidQuRnNnBdyyFhwRC9uwI4XZg= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kg/kLRsV; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kg/kLRsV" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 86652C4CED1; Wed, 5 Feb 2025 14:14:34 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1738764874; bh=FidpCX5GxjvcT+vVJZsxzD/fUKwHxS5XyiCZNAkvy+A=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Kg/kLRsVnpJXWn/B2nZ8RB+eYvAbTXWmf73EIc7Z8lqmI7IBnmS7FZODsMY7nf/vR AAd8sV74hLxr2lZxXuSk0f+60BqUdl7YCZw3Nl4p4y0kFF/125Fx7CKvOODPGNuzB6 9LLpMCR7+aAn9Vm5SRX6ejTH/3+gz0+2zRNqsMhB+9+CjnJ8niQHJDjOxt6R+m2Kaj 8xsJwOFmqjtqFn9oJIhIEypQMscWQNIijygSO+nR1xrD9vIg7TfqOCOZgLGRDUN44A iIZcj+CJpVD2yk45wGuXa0aVUyJA+kQeHZhI8r6iyy9FMgb/n6RnoTZvGx13pD1Htv M1q1ItW7R+AFw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tfgAi-000nOu-17; Wed, 05 Feb 2025 14:14:32 +0000 Date: Wed, 05 Feb 2025 14:14:30 +0000 Message-ID: <86wme4tr5l.wl-maz@kernel.org> From: Marc Zyngier To: Zaid Alali Cc: catalin.marinas@arm.com, will@kernel.org, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, mark.rutland@arm.com, ruanjinjie@huawei.com, oliver.upton@linux.dev, robh@kernel.org, anshuman.khandual@arm.com, james.morse@arm.com, shiqiliu@hust.edu.cn, eahariha@linux.microsoft.com, scott@os.amperecomputing.com, joey.gouly@arm.com, ardb@kernel.org, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] arm64: errata: Add Ampere erratum AC04_CPU_50 workaround alternative In-Reply-To: References: <20250127201829.209258-1-zaidal@os.amperecomputing.com> <87msfbtjyw.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: zaidal@os.amperecomputing.com, catalin.marinas@arm.com, will@kernel.org, puranjay@kernel.org, broonie@kernel.org, mbenes@suse.cz, mark.rutland@arm.com, ruanjinjie@huawei.com, oliver.upton@linux.dev, robh@kernel.org, anshuman.khandual@arm.com, james.morse@arm.com, shiqiliu@hust.edu.cn, eahariha@linux.microsoft.com, scott@os.amperecomputing.com, joey.gouly@arm.com, ardb@kernel.org, yangyicong@hisilicon.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Tue, 04 Feb 2025 21:46:06 +0000, Zaid Alali wrote: > > On Tue, Jan 28, 2025 at 08:34:47AM +0000, Marc Zyngier wrote: > > On Mon, 27 Jan 2025 20:18:29 +0000, > > Zaid Alali wrote: > > > > > > Add an alternative code sequence to work around Ampere erratum > > > AC03_CPU_50 on AmpereOne and Ampere1A. > > > > > > Due to AC03_CPU_50, when ICC_PMR_EL1 should have a value of 0xf0 a > > > direct read of the register will return a value of 0xf8. An incorrect > > > value from a direct read can only happen with the value 0xf0. > > > > Under which precise conditions? Does it equally apply to virtual > > interrupts or SCR_EL3.FIQ==0, for which there is no non-secure shift > > (which I can only assume is the source of the erratum)? Does it > > equally affect G0 and G1 interrupts? > > > > Hi Marc, > > This only occurs when: > When SCR_EL3.FIQ==1 and PE is NOT in EL3/Secure State, > and ICC_PMR_EL1.Priority==LowestPriorityImplemented==0xf8 (highest priority is 0x00). > > Does it equally apply to virtual interrupts or SCR_EL3.FIQ==0? > > Based on this Defect (AArch-21735) and our implementation, it only > affected ICC_PMR_EL1, therefore does not apply to virtual interrupts. Are you saying that this is erratum is *strictly* AARCH-21735? M. -- Without deviation from the norm, progress is not possible.