From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 7079378F5F; Tue, 10 Dec 2024 09:49:40 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733824180; cv=none; b=dyYimnuTji5GTSeQWPAa2ddLj30/UdTELpiLgJVkABSTuQqi1PhOHRB+k27jV4UNwThyIy+/D9xmpLbb/aMnZ9BTN8bvOGO4uYFaIzLUU9NYRGtvA/+XE7rgtebRRirYADjEsNzeHGHn8a+Q8cWRMRYsyCDPmbi+snjcWLvSRdo= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1733824180; c=relaxed/simple; bh=NrY3YRq//HQXc5Zz8ylLbD15FcekagcoyDDQYiTzGEo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=dw0JPeChjugYlrRDBFz5iy4ub/ftKEoIuNcJPHnQowZeb8QeZwHHh9vSRQBFGlMNwZMzsY7F6qr0RwjA6JrdZW+DzQb7BjMSrMAY9DaQKpE5Tb+Si8la1lM3oQVTVsqsMVwP7fC+sk950CNm5aCaMKU6hF88MJFxQdgLRMHRk3g= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=S2l45DES; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="S2l45DES" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 366C8C4CED6; Tue, 10 Dec 2024 09:49:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1733824180; bh=NrY3YRq//HQXc5Zz8ylLbD15FcekagcoyDDQYiTzGEo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=S2l45DESv/WhTR2+g4xv8B9bCTglekRh2uz7K1KY9cusAgjNyf3VQB37WYae7YISP wB4WrPtyg1tCHL/d9X/oNG5ED3D5WFQ3OOvD3/ESvK3pxzy/15jz498m2j82KUpCTl xR4sURDuYLenzKUGh8w+2/IUdRKh0zoy6f1EmYjA2WaqyqsaU8dgOOieuTGpMgOP2s GPbj0H3MhkggU9kCS7x93U9KWPTyVZOuYTNfMh9QEUvJCrhhbbdWvdWCq7h+TAWuy0 0bZG7wYvcFsziA3r+E4xVY3VC6kK3r9tJN46z5HwzOG7vo2DEzP0Qsp6Uit/VkZ83y /0evu/CC5U0Xw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tKws5-002DVo-DT; Tue, 10 Dec 2024 09:49:37 +0000 Date: Tue, 10 Dec 2024 09:49:37 +0000 Message-ID: <86wmg7sw9a.wl-maz@kernel.org> From: Marc Zyngier To: Oliver Upton Cc: kvmarm@lists.linux.dev, Joey Gouly , Suzuki K Poulose , Zenghui Yu , Mingwei Zhang , Colton Lewis , Raghavendra Rao Ananta , Catalin Marinas , Will Deacon , Mark Rutland , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org Subject: Re: [RFC PATCH 05/14] KVM: arm64: Always allow fixed cycle counter In-Reply-To: References: <20241203193220.1070811-1-oliver.upton@linux.dev> <20241203193220.1070811-6-oliver.upton@linux.dev> <87ldwwsbad.wl-maz@kernel.org> <87ikrzstt1.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: oliver.upton@linux.dev, kvmarm@lists.linux.dev, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, mizhang@google.com, coltonlewis@google.com, rananta@google.com, catalin.marinas@arm.com, will@kernel.org, mark.rutland@arm.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 04 Dec 2024 21:56:58 +0000, Oliver Upton wrote: > > On Wed, Dec 04, 2024 at 09:04:26AM +0000, Marc Zyngier wrote: > > On Tue, 03 Dec 2024 22:32:38 +0000, > > Oliver Upton wrote: > > > > More importantly, the current filtering works in terms of events, and > > > > not in terms of counters. > > > > > > > > Instead of changing the ABI, how about simply not supporting filtering > > > > on such non-compliant HW? Surely that would simplify a few things. > > > > > > Yeah, that sounds reasonable. Especially if we allow programmable event > > > counters where the event ID space doesn't match the architecture. > > > > Another thing I have been wondering is if a slightly better approach > > would be to move some of the handling to the PMU driver itself, and > > let it emulate PMUv3 if it can. This would allow conversion of event > > numbers in situ rather than polluting the PMUv3 code in KVM. > > Sure, but I think the actual event fed into perf_event_create_kernel_counter() > should be the correct hardware event, not a PMUv3 event reinterpreted > behind the scenes. Otherwise, we'd need to devise an alternate config encoding > for PMUv3-like events since the event ID spaces overlap. > > I'm thinking this could be a helper in the arm_pmu struct that takes a > PMUv3 event and spits out (in this case) an M1 event. The resulting KVM > code would be miniscule, like: > > u64 kvm_map_pmu_event(struct kvm *kvm, u64 eventsel) > { > struct arm_pmu *pmu = kvm->arch.arm_pmu; > > if (!pmu->map_pmuv3_event) > return eventsel; > > return pmu->map_pmuv3_event(eventsel); > } > > static void kvm_pmu_create_perf_event(struct kvm_pmc *pmc) > { > > [...] > > attr.config = kvm_map_pmu_event(vcpu->kvm, eventsel); > event = perf_event_create_kernel_counter(&attr, ...); > } > > We could even have the M1 PMU driver populate arm_pmu->pmceid_bitmap > with the events it knows about and get PMCEID emulation for free. CONFIG_PMUv3_COMPAT? ;-) I think this is probably the less intrusive thing to do for KVM (outside of the butt-ugly trap decoding thingy), and it squarely puts the responsibility on the PMU driver to expose something that makes sense in a given context. Thanks, M. -- Without deviation from the norm, progress is not possible.