From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id D71E41F8690; Wed, 8 Jan 2025 10:58:20 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736333901; cv=none; b=bL81UvVHPghim8v8beTITnItELeovGDh7ec7hnWHddViND726VIX7ealk7ZmRRSpGoNe1Y/QJxhD/iG5w7Z3ZDaa9jJwIEYE15duYVkF0Tn5De9Du3YqotHGojBdHhPnlv1HgvGvyHkxG7Vur2dvLOegooc22FSi2r/R9sd4Ni0= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1736333901; c=relaxed/simple; bh=ibQrjcysOmiREdLmToxpMoGiX7/kWkXu5VNgua+RmGo=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=Su6ix/0EPM/9CUKjqiJwzzQLGMgPFkx6M1vJvuTmsE8CumxSPp8F4t/mWL/L87BqQdp0o05OVSOP7o8SgNC2E6JK2Fj9/qmSKbH5g4ltzyMFgaGgKdtXHvAMkUzHBGcqOPAavOMCwbFHpo5QGS1EYVORvTITGGDpsipLp4eQidM= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=Kt4qgpfC; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="Kt4qgpfC" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 699F6C4CEDD; Wed, 8 Jan 2025 10:58:20 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1736333900; bh=ibQrjcysOmiREdLmToxpMoGiX7/kWkXu5VNgua+RmGo=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=Kt4qgpfCjkrnbJhh+IgACng1RwGLY7VeQSXzYmbke/hzPsDWFcsPs+TEXPSY3rfVO Q+rWx7jmBTD+RxYmAhpWmBYSN9CFaB0jcqRGQHF9uBQkIr1wl9T2Fxf4lls4B2/KLI bShYL7TzFM5XLtQUlAvcjmF62o0DO6/7QgniGZr0t+v4n+Pgp32GRdgSz00fRIv/ng 0mHmeVN46YX5tKNKOgMrBhKBisrP2PZuWTkCM8VUBIGv5jZ8mSOB5nNrJp9y0xRPuA Kas5EHXe/WzG9W8kc6PFiRujcUMBGF2Vh3AvvV3ZbX35E1Ab7gAylHkqnvqgViW5za xJZPkZ84nXM+w== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1tVTlS-00A6tJ-AE; Wed, 08 Jan 2025 10:58:18 +0000 Date: Wed, 08 Jan 2025 10:58:16 +0000 Message-ID: <86y0zlwp13.wl-maz@kernel.org> From: Marc Zyngier To: Zhiyuan Dai Cc: oliver.upton@linux.dev, catalin.marinas@arm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org Subject: Re: [PATCH] KVM: arm64: vgic: Update some comments to improve the code readability In-Reply-To: <20250108103919.66572-1-daizhiyuan@phytium.com.cn> References: <20250108103919.66572-1-daizhiyuan@phytium.com.cn> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/29.4 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: daizhiyuan@phytium.com.cn, oliver.upton@linux.dev, catalin.marinas@arm.com, joey.gouly@arm.com, suzuki.poulose@arm.com, yuzenghui@huawei.com, kvmarm@lists.linux.dev, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false [Fixing Suzuki's address] On Wed, 08 Jan 2025 10:39:19 +0000, Zhiyuan Dai wrote: > > This patch updates the comments in the vgic_v3_queue_sgi function > to improve the readability of the code. > > Signed-off-by: Zhiyuan Dai > --- > arch/arm64/kvm/vgic/vgic-mmio-v3.c | 7 ++++++- > 1 file changed, 6 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kvm/vgic/vgic-mmio-v3.c b/arch/arm64/kvm/vgic/vgic-mmio-v3.c > index ae4c0593d114..f3b328373869 100644 > --- a/arch/arm64/kvm/vgic/vgic-mmio-v3.c > +++ b/arch/arm64/kvm/vgic/vgic-mmio-v3.c > @@ -1040,8 +1040,13 @@ static void vgic_v3_queue_sgi(struct kvm_vcpu *vcpu, u32 sgi, bool allow_group1) > irq->pending_latch = true; > vgic_queue_irq_unlock(vcpu->kvm, irq, flags); > } else { > - /* HW SGI? Ask the GIC to inject it */ > int err; > + > + /* > + * With GICv4.1, vSGI can be directly injected. > + * So let's pretend that they are HW interrupts, > + * tied to a host IRQ. > + */ > err = irq_set_irqchip_state(irq->host_irq, > IRQCHIP_STATE_PENDING, > true); Do you really see this as an improvement? I don't think we need to paraphrase the code, which is pretty obvious. If anything, I'd happily remove the *existing* comment. M. -- Without deviation from the norm, progress is not possible.