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From: Marc Zyngier <maz@kernel.org>
To: Manivannan Sadhasivam <mani@kernel.org>
Cc: Qiang Yu <qiang.yu@oss.qualcomm.com>,
	tglx@linutronix.de, linux-kernel@vger.kernel.org
Subject: Re: MSIs not freed in GICv3 ITS driver
Date: Wed, 01 Apr 2026 17:08:15 +0100	[thread overview]
Message-ID: <86zf3m3bps.wl-maz@kernel.org> (raw)
In-Reply-To: <4lidir7hbrtwioxujeqyulk2e5wcjsy4qmlqjprncbogrepylz@wdwveqxidrxj>

On Wed, 01 Apr 2026 13:01:49 +0100,
Manivannan Sadhasivam <mani@kernel.org> wrote:
> 
> On Wed, Apr 01, 2026 at 09:15:30AM +0100, Marc Zyngier wrote:
> > On Wed, 01 Apr 2026 08:59:02 +0100,
> > Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > 
> > > On Mon, Mar 30, 2026 at 09:17:10AM +0100, Marc Zyngier wrote:
> > > > On Tue, 03 Mar 2026 09:26:32 +0000,
> > > > Manivannan Sadhasivam <mani@kernel.org> wrote:
> > > > > 
> > > > > The above issue should be applicable to other MSI controller drivers as well,
> > > > > not just DWC.
> > > > 
> > > > The core issue is not with the irqchips, but with the MSI subsystem.
> > > > 
> > > > Multi-MSI devices should always result in a strict power-of-2
> > > > allocation, because that's all the HW supports. Yet, we let drivers
> > > > request a stupid number of interrupts.
> > > > 
> > > > I can see two outcomes: either we force the allocation to the next 2^
> > > > value, or we return an error to the caller. The first one costs memory
> > > > (extra irq descriptors), the latter forces people to fix their crap.
> > > > 
> > > > I'm tempted to propose the latter.
> > > > 
> > > 
> > > That might cause a lot of regressions I believe. IMO, safe bet would be to
> > > handle the power of 2 allocations inside the irqchip drivers.
> > 
> > What part of "this is a violation of the PCI spec" did you miss? I
> > didn't realise we were in the business of adding crap just because
> > endpoint drivers are broken.
> > 
> 
> I agree that the endpoint drivers requesting non power-of-2 MSIs is flawed in
> the first place. But a lot of drivers do:
> 
> pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_INTX);
> or
> pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES);
> 
> This is so far working for these drivers and *may* suddenly break if the irqchip
> drivers start returning errors. I was just trying to avoid that
> situation.

1 *IS* a power of two. Any driver that does that is perfectly fine.

A driver that does

pci_alloc_irq_vectors(pdev, 1, 7, PCI_IRQ_MSI);

or

pci_alloc_irq_vectors(pdev, 7, 7, PCI_IRQ_MSI);

is broken. *That* is what the PCI core code should enforce.

	M.

-- 
Without deviation from the norm, progress is not possible.

  reply	other threads:[~2026-04-01 16:08 UTC|newest]

Thread overview: 19+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2024-07-08 15:39 MSIs not freed in GICv3 ITS driver Manivannan Sadhasivam
2024-07-08 17:31 ` Marc Zyngier
2024-07-09 17:37   ` Manivannan Sadhasivam
2024-07-09 19:24     ` Marc Zyngier
2024-07-21  8:50       ` Manivannan Sadhasivam
2026-01-16 15:03         ` Manivannan Sadhasivam
2026-02-19 16:54           ` Marc Zyngier
2026-02-25  9:34             ` Qiang Yu
2026-02-26 13:39               ` Marc Zyngier
2026-03-03  5:22                 ` Qiang Yu
2026-03-03  9:26                 ` Manivannan Sadhasivam
2026-03-30  8:17                   ` Marc Zyngier
2026-04-01  7:59                     ` Manivannan Sadhasivam
2026-04-01  8:15                       ` Marc Zyngier
2026-04-01 12:01                         ` Manivannan Sadhasivam
2026-04-01 16:08                           ` Marc Zyngier [this message]
2026-04-01 17:37                             ` Manivannan Sadhasivam
2026-04-07 10:45                             ` Thomas Gleixner
2026-04-07 12:18                               ` Manivannan Sadhasivam

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