From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 61BE432AAB2 for ; Wed, 1 Apr 2026 16:08:18 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775059698; cv=none; b=QL8rCQPodF/4HBJOGnv+wYoyVLZk6PNXaV9SaCflIYIOf1SXvX+kCeYPrTI+ZzWquc8rHL9gDaOk+5nP6d0sTW39I0slSrWex47+7+t3BtBJCApBT9pYvcgnh3aF9yheKv/qbaZmsPnWFmDxLKl+M0A9Y19EIlv52Vnt8TQUuHA= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1775059698; c=relaxed/simple; bh=o7QrzbOgNKdNB2CPB+8q8PHzcp5tZITBLheaZ+EM+TQ=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=AWZ11LC6OI8Tnc/V+ZtlLQyVHec0PaVPjsP/3P3u1E7qSUyknNlfmb+i2P4oi9c4d0FBjJiiGRVaebolhiDzY4DhFHirSp5VwZvuqhd0LFFd4FL6SlZsEFxI2Uj7L0V0FhMGidp3/ulEKistRLQ3JooMUK5RcNlcNLTAvnfgvE8= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=ux1c3rA9; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="ux1c3rA9" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 08729C4CEF7; Wed, 1 Apr 2026 16:08:17 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1775059698; bh=o7QrzbOgNKdNB2CPB+8q8PHzcp5tZITBLheaZ+EM+TQ=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=ux1c3rA9K2P79PzrO4NVgXFyNxdBb7Th6sxNHijhMVhaDGDbjE7a9XwZXRzJaM7zL cUSb2I1lQe7ALOfxKtydtC5avTMrjPL9uB+8AbhswbVQcGLgdj4tLlrFdirzWA9An/ XPq1ov0hsDIkF/56LbUNN2EhfP1R2IOeDUPq3Ytj9lOxVY4OYuyzqjQ6MdT7j8JO9W X09G8FZurx1R7R3LGoUNCeP9wMi8K5r9WbKYzejV7MrEIyiOil6K5zvkncsZIbSVFZ Jnto3g0mH2PatPJ6iSQCP0oqEkoFJDaVV8Tiy8wntK6n4xMDFNjlMSWLwjlXBz3flT 5wJXuertLbKCg== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w7y75-00000007wGz-3pZs; Wed, 01 Apr 2026 16:08:16 +0000 Date: Wed, 01 Apr 2026 17:08:15 +0100 Message-ID: <86zf3m3bps.wl-maz@kernel.org> From: Marc Zyngier To: Manivannan Sadhasivam Cc: Qiang Yu , tglx@linutronix.de, linux-kernel@vger.kernel.org Subject: Re: MSIs not freed in GICv3 ITS driver In-Reply-To: <4lidir7hbrtwioxujeqyulk2e5wcjsy4qmlqjprncbogrepylz@wdwveqxidrxj> References: <877cdupdvu.wl-maz@kernel.org> <20240721085032.GL1908@thinkpad> <4pdu25dnnqegnd67zf4ftfvwc57bn67kp7mj2gk2cywc3hdcvr@eydar5gvuwtu> <86wm08ad2y.wl-maz@kernel.org> <865x7jaajs.wl-maz@kernel.org> <86cy0l4tq1.wl-maz@kernel.org> <864ilv3xlp.wl-maz@kernel.org> <4lidir7hbrtwioxujeqyulk2e5wcjsy4qmlqjprncbogrepylz@wdwveqxidrxj> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: mani@kernel.org, qiang.yu@oss.qualcomm.com, tglx@linutronix.de, linux-kernel@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Wed, 01 Apr 2026 13:01:49 +0100, Manivannan Sadhasivam wrote: > > On Wed, Apr 01, 2026 at 09:15:30AM +0100, Marc Zyngier wrote: > > On Wed, 01 Apr 2026 08:59:02 +0100, > > Manivannan Sadhasivam wrote: > > > > > > On Mon, Mar 30, 2026 at 09:17:10AM +0100, Marc Zyngier wrote: > > > > On Tue, 03 Mar 2026 09:26:32 +0000, > > > > Manivannan Sadhasivam wrote: > > > > > > > > > > The above issue should be applicable to other MSI controller drivers as well, > > > > > not just DWC. > > > > > > > > The core issue is not with the irqchips, but with the MSI subsystem. > > > > > > > > Multi-MSI devices should always result in a strict power-of-2 > > > > allocation, because that's all the HW supports. Yet, we let drivers > > > > request a stupid number of interrupts. > > > > > > > > I can see two outcomes: either we force the allocation to the next 2^ > > > > value, or we return an error to the caller. The first one costs memory > > > > (extra irq descriptors), the latter forces people to fix their crap. > > > > > > > > I'm tempted to propose the latter. > > > > > > > > > > That might cause a lot of regressions I believe. IMO, safe bet would be to > > > handle the power of 2 allocations inside the irqchip drivers. > > > > What part of "this is a violation of the PCI spec" did you miss? I > > didn't realise we were in the business of adding crap just because > > endpoint drivers are broken. > > > > I agree that the endpoint drivers requesting non power-of-2 MSIs is flawed in > the first place. But a lot of drivers do: > > pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_MSI | PCI_IRQ_INTX); > or > pci_alloc_irq_vectors(pdev, 1, 1, PCI_IRQ_ALL_TYPES); > > This is so far working for these drivers and *may* suddenly break if the irqchip > drivers start returning errors. I was just trying to avoid that > situation. 1 *IS* a power of two. Any driver that does that is perfectly fine. A driver that does pci_alloc_irq_vectors(pdev, 1, 7, PCI_IRQ_MSI); or pci_alloc_irq_vectors(pdev, 7, 7, PCI_IRQ_MSI); is broken. *That* is what the PCI core code should enforce. M. -- Without deviation from the norm, progress is not possible.