From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 36D1736E478 for ; Mon, 23 Mar 2026 13:37:49 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774273069; cv=none; b=m2uvBYy+WbZ65LwJdDrmrxqbV0QsgkthPBE6bw5Q/FssSEVbIUhB8RR5CLwyj8LT+eFg0I+OtP7eTmSy8B3U7zPCeEiLd0ls2HqaUIXX9SdglV1FBR8cbEl1yhR0TiXhMV9fsQOCI4z3Fg1wTgxapOw6HGaRUxe/RYiVAgflaaQ= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1774273069; c=relaxed/simple; bh=2cqR1rN3wK7fWYemJafbvd7wsEJefJp1THcpsU4X2ng=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=kbnH+LGn3y40DxngU7WwbIJSj7IxU9eJ1cgjsmYcbSWrzDUV62TvwaicJ6tk7UUmlsNkRFSPB1XzR1F5ls2FEGk32oLLLfGcQ4NKiLwv3xGGoPXIjgzN9Gm4MSSZ/T79xP6pqD7cFp1cNqwXALWegYUcFiL51XgI0WchTjYZ5Og= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=DrF5ugQJ; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="DrF5ugQJ" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 0F086C4CEF7; Mon, 23 Mar 2026 13:37:49 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1774273069; bh=2cqR1rN3wK7fWYemJafbvd7wsEJefJp1THcpsU4X2ng=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=DrF5ugQJ/IWrHkq0VY/MHvgM5WfBRYnOr5dTR4vao4Vdb49JZmdRRZG8Tnl3tYFAh 0jfea3lO09beJYycRVCN/U2Tc33a3s2LWiuWlNq7GQ4KPBRrxnR1T26PTWtjxpkRQ3 1tOowqZrTCRKM6kESTudRPLlVsj6rDT54AHP5WD67urZbJwHORlGuXEEiw6T/OSoZQ olpY9OJodC52k9kpJbE9W9A2GXbb5Dy9/PV2UMmq5aa6tqKGdchhj+Ptii34Hzer9W WF7/PoYgMg6shpzKclhV5xd39qE6gdKbB0NDl1hpMcga48rVkPhvtYIyNwJtFPo+xQ Mre78LxuvPAHw== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.98.2) (envelope-from ) id 1w4fTW-00000004kDk-3Iyr; Mon, 23 Mar 2026 13:37:46 +0000 Date: Mon, 23 Mar 2026 13:37:46 +0000 Message-ID: <86zf3y4qfp.wl-maz@kernel.org> From: Marc Zyngier To: Javier Achirica Cc: linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@kernel.org Subject: Re: [PATCH v1] irqchip: fix mask alignment in gic-v2m In-Reply-To: References: User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: jachirica@gmail.com, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, tglx@kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Sat, 21 Mar 2026 14:12:16 +0000, Javier Achirica wrote: > > commit 2ef3886ce626dcdab0cbc452dbbebc19f57133d8 ("irqchip/gic-v2m: Handle > Multiple MSI base IRQ Alignment") introduced a regression in kernel 6.12.58 > affecting PCIe devices using GICv2m MSI on a Qualcomm (arm64) platform. > > It uses nr_irqs parameter to generate a mask to align the MSI base address, > but this mask isn't properly generated when nr_irqs isn't a power of two. > This bug was found while adding support for the TCL HH500V router in OpenWrt. > > This patch fixes the issue, can be cleanly applied to the 6.12.x tree and, > with a small fuzz, to 7.0.x. > > Signed-off-by: Javier Achirica > Cc: stable@vger.kernel.org > --- > --- a/drivers/irqchip/irq-gic-v2m.c 2026-03-20 09:45:22.170192561 +0100 > +++ b/drivers/irqchip/irq-gic-v2m.c 2026-03-20 09:45:26.284210783 +0100 > @@ -158,7 +158,7 @@ > struct v2m_data *v2m = NULL, *tmp; > int hwirq, i, err = 0; > unsigned long offset; > - unsigned long align_mask = nr_irqs - 1; > + unsigned long align_mask = roundup_pow_of_two(nr_irqs) - 1; > > spin_lock(&v2m_lock); > list_for_each_entry(tmp, &v2m_nodes, entry) { > This looks wrong for a bunch of reasons: - you're hacking the allocation path, but not the free path -- what could possibly go wrong? - nr_irqs not being a power of two to start with is more indicative of a bug somewhere else in the system. The only case where we allocate more than a single IRQ at a time is for Multi-MSI, and that is definitely a power-of-two construct. I have seen other reports, all concerning QC based HW allocating silly (aka non Po2) numbers of interrupts for Nulti-MSI devices, and I think we should instead address the root cause, most likely in the PCI code. Thanks, M. -- Without deviation from the norm, progress is not possible.