From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 2BB6FEB64DC for ; Tue, 18 Jul 2023 09:27:05 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231307AbjGRJ1D (ORCPT ); Tue, 18 Jul 2023 05:27:03 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:34546 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S232310AbjGRJ0x (ORCPT ); Tue, 18 Jul 2023 05:26:53 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 8A0F610C0 for ; Tue, 18 Jul 2023 02:26:41 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0ED6D614BD for ; Tue, 18 Jul 2023 09:26:41 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 668A2C433C7; Tue, 18 Jul 2023 09:26:40 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1689672400; bh=P+0tnFAUBpCUj8Mt4/Kizy81HhkyMlHz8rGGSKFzB80=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=PzHrKGNoAnNHwZTX0kXJ+CtXWEHZ90ZBM0nVxjNaze18v3HxVDzpvWeqZ2Nm1P5Q3 XGQlWjlBcGk3l9fzer/2KUe5tcU1XIgs0cQvRj7nNWPICvAZiatzzRiS6MuBo814cS CiiijCcJU5aZzKOc3SI+bmBzcsqadN/Cv2E9UNnTMjvbrHBviKa+l3rgnP6fKzF8H6 703N+S1EaKCGNIEkf9xsvV8aKDDWOCN2YG4jo8l4E5s62kKgLW+Eh4nULUAP3GyKmb DAew9SljnHOKh7Hz2zxN3rTtNVLLMYjex+KwRrFs2nTkhFPs1UuWZDvhlip9OKjBFI G9ld7vh9LM6jQ== Received: from sofa.misterjones.org ([185.219.108.64] helo=goblin-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1qLgyc-00Dzh1-03; Tue, 18 Jul 2023 10:26:38 +0100 Date: Tue, 18 Jul 2023 10:26:37 +0100 Message-ID: <86zg3ttvsi.wl-maz@kernel.org> From: Marc Zyngier To: Samuel Holland Cc: Palmer Dabbelt , Paul Walmsley , Samuel Holland , Thomas Gleixner , linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org Subject: Re: [PATCH] irqchip/sifive-plic: Avoid clearing the per-hart enable bits In-Reply-To: <20230717185841.1294425-1-samuel.holland@sifive.com> References: <20230717185841.1294425-1-samuel.holland@sifive.com> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/28.2 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: samuel.holland@sifive.com, palmer@dabbelt.com, paul.walmsley@sifive.com, samuel@sholland.org, tglx@linutronix.de, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Mon, 17 Jul 2023 19:58:40 +0100, Samuel Holland wrote: > > Writes to the PLIC completion register are ignored if the enable bit for > that (interrupt, hart) combination is cleared. This leaves the interrupt > in a claimed state, preventing it from being triggered again. > > Originally, the enable bit was cleared in the .irq_mask operation, and > commit 69ea463021be ("irqchip/sifive-plic: Fixup EOI failed when masked") > added a workaround for this issue. Later, commit a1706a1c5062 > ("irqchip/sifive-plic: Separate the enable and mask operations") moved > toggling the enable bit to the .irq_enable/.irq_disable operations and > removed the workaround. > > However, there are still places where .irq_disable can be called from > inside the hard IRQ handler, for example in irq_pm_check_wakeup(). As a > result, this issue causes an interrupt to get stuck in a claimed state > after being used to wake the system from s2idle. > > There is no real benefit to implementing the .irq_enable/.irq_disable > operations using the enable bits. In fact, the existing mask/unmask > implementation using the threshold register is already more efficient, > as it requires no read/modify/write cycles. So let's leave the enable > bits set for the lifetime of the IRQ, using them only to control its > affinity. Side question, which doesn't affect this patch: what happens with interrupts that are firing while the interrupt is in a disabled state? It's fine for levels, but what of edge interrupts? My reading of the spec is that it is the role of the "gateway" to hold the signal, and that this is upstream of the PLIC itself, so it *should* be fine, but I'd like confirmation on that. Thanks, M. -- Without deviation from the norm, progress is not possible.