[PATCH 1/5] dt-bindings: irq: Add Qualcomm MSM VIC binding

[PATCH 1/5] dt-bindings: irq: Add Qualcomm MSM VIC binding

[j0sh1x]

Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>
---
 .../interrupt-controller/qcom,msm-vic.yaml    | 72 +++++++++++++++++++
 1 file changed, 72 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml

diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml
new file mode 100644
index 000000000000..5bf281f72fe0
--- /dev/null
+++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: GPL-2.0
+# qualcomm,msm-vic.yaml - Device Tree binding for Qualcomm MSM VIC interrupt controller
+
+description: >
+  Qualcomm MSM VIC (Vector Interrupt Controller). This interrupt controller
+  handles normal and wakeup interrupts and supports mapping to the
+  Qualcomm SMSM system.
+
+compatible: ["qcom,msm-vic"]
+
+properties:
+  interrupt-controller:
+    description: "Identifies this node as an interrupt controller"
+    required: true
+    type: boolean
+
+  #interrupt-cells:
+    description: "Specifies the number of cells needed to encode an interrupt"
+    required: true
+    type: integer
+    default: 1
+
+  reg:
+    description: "Base address and size of the VIC registers"
+    required: true
+    type: reg
+
+  num-irqs:
+    description: "Total number of interrupts supported by this VIC"
+    required: true
+    type: integer
+
+  num-gpio-irqs:
+    description: "Number of GPIO interrupts routed through this VIC"
+    required: true
+    type: integer
+
+  vic-num-regs:
+    description: "Number of VIC register banks"
+    required: true
+    type: integer
+
+  irq-mapping:
+    description:
+      Mapping of VIC IRQ numbers to SMSM wakeup channels. Each mapping
+      consists of two integers: <VIC IRQ> <SMSM channel>.  
+      "SMSM_FAKE_IRQ" can be used for virtual/fake wakeup interrupts.
+    required: true
+    type: list
+    items:
+      - vic-irq: integer
+        smsm-channel: integer
+
+examples:
+  - |
+    #include <dt-bindings/interrupt-controller/qcom-vic.h>
+    intc: interrupt-controller@ac000000 {
+        compatible = "qcom,msm-vic";
+        interrupt-controller;
+        #interrupt-cells = <1>;
+        reg = <0xac000000 0x1000>;
+        num-irqs = <64>;
+        num-gpio-irqs = <165>;
+        vic-num-regs = <2>;
+        irq-mapping = <
+            17 1   /* INT_MDDI_EXT -> SMSM 1 */
+            16 2   /* INT_MDDI_PRI -> SMSM 2 */
+            18 3   /* INT_MDDI_CLIENT -> SMSM 3 */
+            15 4   /* INT_USB_OTG -> SMSM 4 */
+            0 SMSM_FAKE_IRQ   /* INT_A9_M2A_0 -> SMSM_FAKE_IRQ */
+        >;
+    }
\ No newline at end of file
-- 
2.51.0

[PATCH 2/5] irqchip: Add Qualcomm MSM VIC driver

[j0sh1x]

Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>
---
 drivers/irqchip/irq-msm-vic.c | 361 ++++++++++++++++++++++++++++++++++
 1 file changed, 361 insertions(+)
 create mode 100644 drivers/irqchip/irq-msm-vic.c

diff --git a/drivers/irqchip/irq-msm-vic.c b/drivers/irqchip/irq-msm-vic.c
new file mode 100644
index 000000000000..7e7f7be3ad6d
--- /dev/null
+++ b/drivers/irqchip/irq-msm-vic.c
@@ -0,0 +1,361 @@
+// SPDX-License-Identifier: GPL-2.0 OR MIT
+/*
+ * Copyright (C) 2007 Google, Inc.
+ * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
+ * Copyright (c) 2024, Htc Leo Revival Project
+ *
+ * This software is licensed under the terms of the GNU General Public
+ * License version 2, as published by the Free Software Foundation, and
+ * may be copied, distributed, and modified under those terms.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ */
+
+#include <linux/init.h>
+#include <linux/module.h>
+#include <linux/sched.h>
+#include <linux/interrupt.h>
+#include <linux/ptrace.h>
+#include <linux/timer.h>
+#include <linux/irq.h>
+#include <linux/irqchip.h>
+#include <linux/io.h>
+#include <linux/of.h>
+#include <linux/of_address.h>
+#include <linux/of_irq.h>
+#include <linux/of_platform.h>
+#include <linux/cacheflush.h>
+
+#include <asm/exception.h>
+#include <asm/irq.h>
+
+#include <dt-bindings/interrupt-controller/qcom-vic.h>
+
+static u32 msm_irq_smsm_wake_enable[2];
+struct msm_irq_shadow {
+	u32 int_en[2];
+	u32 int_type;
+	u32 int_polarity;
+	u32 int_select;
+};
+
+static struct msm_irq_shadow *msm_irq_shadow_reg;
+static u32 *msm_irq_idle_disable;
+
+struct msm_irq_map {
+	u32 irq;
+	u8 smsm;
+};
+
+struct vic_device {
+	void __iomem *base;
+	struct irq_domain *domain;
+	u32				msm_nr_irqs;
+	u32				nr_vic_irqs;
+	u32				nr_gpio_irqs;
+	u32				vic_num_regs;
+	struct msm_irq_map *irq_map;
+	int irq_map_count;
+};
+
+static struct vic_device vic_data;
+
+static int msm_irq_to_smsm(u32 irq)
+{
+	int i;
+
+	if (!vic_data.irq_map)
+		return -EINVAL;
+
+	for (i = 0; i < vic_data.irq_map_count; i++) {
+		if (vic_data.irq_map[i].irq == irq)
+			return vic_data.irq_map[i].smsm;
+		}
+
+	return -ENOENT;
+}
+
+void set_irq_flags(unsigned int irq, unsigned int iflags);
+
+void set_irq_flags(unsigned int irq, unsigned int iflags)
+{
+	unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
+
+	if (irq >= vic_data.msm_nr_irqs) {
+		pr_err("Trying to set irq flags for IRQ%d\n", irq);
+		return;
+	}
+
+	if (iflags & IRQF_VALID)
+		clr |= IRQ_NOREQUEST;
+	if (iflags & IRQF_PROBE)
+		clr |= IRQ_NOPROBE;
+	if (!(iflags & IRQF_NOAUTOEN))
+		clr |= IRQ_NOAUTOEN;
+	/* Order is clear bits in "clr" then set bits in "set" */
+	irq_modify_status(irq, clr, set & ~clr);
+}
+EXPORT_SYMBOL_GPL(set_irq_flags);
+
+static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
+{
+	for (int i = 0; i < vic_data.vic_num_regs; i++)
+		writel(val, base + (i * 4));
+}
+
+static void msm_irq_ack(struct irq_data *d)
+{
+	void __iomem *reg = VIC_INT_TO_REG_ADDR(vic_data.base + VIC_INT_CLEAR0, d->irq);
+
+	writel(1 << (d->irq & 31), reg);
+}
+
+static void msm_irq_mask(struct irq_data *d)
+{
+	void __iomem *reg = VIC_INT_TO_REG_ADDR(vic_data.base + VIC_INT_ENCLEAR0, d->irq);
+	unsigned int index = VIC_INT_TO_REG_INDEX(d->irq);
+	u32 mask = 1UL << (d->irq & 31);
+	int smsm_irq = msm_irq_to_smsm(d->irq);
+
+	msm_irq_shadow_reg[index].int_en[0] &= ~mask;
+	writel(mask, reg);
+	if (smsm_irq == 0) {
+		msm_irq_idle_disable[index] &= ~mask;
+	} else {
+		mask = 1UL << (smsm_irq - 1);
+		msm_irq_smsm_wake_enable[0] &= ~mask;
+	}
+}
+
+static void msm_irq_unmask(struct irq_data *d)
+{
+	void __iomem *reg = VIC_INT_TO_REG_ADDR(vic_data.base + VIC_INT_ENSET0, d->irq);
+	unsigned int index = VIC_INT_TO_REG_INDEX(d->irq);
+	u32 mask = 1UL << (d->irq & 31);
+	int smsm_irq = msm_irq_to_smsm(d->irq);
+
+	msm_irq_shadow_reg[index].int_en[0] |= mask;
+	writel(mask, reg);
+
+	if (smsm_irq == 0) {
+		msm_irq_idle_disable[index] |= mask;
+	} else {
+		mask = 1UL << (smsm_irq - 1);
+		msm_irq_smsm_wake_enable[0] |= mask;
+	}
+}
+
+static int msm_irq_set_wake(struct irq_data *d, unsigned int on)
+{
+	unsigned int index = VIC_INT_TO_REG_INDEX(d->irq);
+	u32 mask = 1UL << (d->irq & 31);
+	int smsm_irq = msm_irq_to_smsm(d->irq);
+
+	if (smsm_irq == 0) {
+		pr_err("%s: bad wakeup irq %d\n", __func__, d->irq);
+		return -EINVAL;
+	}
+	if (on)
+		msm_irq_shadow_reg[index].int_en[1] |= mask;
+	else
+		msm_irq_shadow_reg[index].int_en[1] &= ~mask;
+
+	if (smsm_irq == SMSM_FAKE_IRQ)
+		return 0;
+
+	mask = 1UL << (smsm_irq - 1);
+	if (on)
+		msm_irq_smsm_wake_enable[1] |= mask;
+	else
+		msm_irq_smsm_wake_enable[1] &= ~mask;
+	return 0;
+}
+
+static int msm_irq_set_type(struct irq_data *d, unsigned int flow_type)
+{
+	void __iomem *treg = VIC_INT_TO_REG_ADDR(vic_data.base + VIC_INT_TYPE0, d->irq);
+	void __iomem *preg = VIC_INT_TO_REG_ADDR(vic_data.base + VIC_INT_POLARITY0, d->irq);
+	unsigned int index = VIC_INT_TO_REG_INDEX(d->irq);
+	int b = 1 << (d->irq & 31);
+	u32 polarity;
+	u32 type;
+
+	polarity = msm_irq_shadow_reg[index].int_polarity;
+	if (flow_type & (IRQF_TRIGGER_FALLING | IRQF_TRIGGER_LOW))
+		polarity |= b;
+	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_HIGH))
+		polarity &= ~b;
+	writel(polarity, preg);
+	msm_irq_shadow_reg[index].int_polarity = polarity;
+
+	type = msm_irq_shadow_reg[index].int_type;
+	if (flow_type & (IRQF_TRIGGER_RISING | IRQF_TRIGGER_FALLING)) {
+		type |= b;
+		irq_set_handler_locked(d, handle_edge_irq);
+	}
+	if (flow_type & (IRQF_TRIGGER_HIGH | IRQF_TRIGGER_LOW)) {
+		type &= ~b;
+		irq_set_handler_locked(d, handle_level_irq);
+	}
+	writel(type, treg);
+	msm_irq_shadow_reg[index].int_type = type;
+	return 0;
+}
+
+static inline void msm_vic_handle_irq(void __iomem *base_addr, struct pt_regs
+		*regs)
+{
+	u32 irqnr;
+
+	do {
+		/* VIC_IRQ_VEC_RD has irq# or old irq# if the irq has been handled
+		 * VIC_IRQ_VEC_PEND_RD has irq# or -1 if none pending *but* if you
+		 * just read VIC_IRQ_VEC_PEND_RD you never get the first irq for some reason
+		 */
+		irqnr = readl_relaxed(base_addr + VIC_IRQ_VEC_RD);
+		irqnr = readl_relaxed(base_addr + VIC_IRQ_VEC_PEND_RD);
+		if (irqnr == -1)
+			break;
+		handle_IRQ(irqnr, regs);
+	} while (1);
+}
+
+/* enable imprecise aborts */
+static inline void local_cpsie_enable(void)
+{
+	asm volatile("cpsie a" : : : "memory");
+}
+
+static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
+{
+	local_cpsie_enable();// local_abt_enable()?
+	msm_vic_handle_irq(vic_data.base, regs);
+}
+
+static struct irq_chip msm_irq_chip = {
+	.name          = "msm",
+	.irq_disable   = msm_irq_mask,
+	.irq_ack       = msm_irq_ack,
+	.irq_mask      = msm_irq_mask,
+	.irq_unmask    = msm_irq_unmask,
+	.irq_set_wake  = msm_irq_set_wake,
+	.irq_set_type  = msm_irq_set_type,
+};
+
+static int msm_vic_parse_irq_mapping(struct device_node *np, struct msm_irq_map **map, int *count)
+{
+	const __be32 *prop;
+	int len, i;
+
+	prop = of_get_property(np, "irq-mapping", &len);
+	if (!prop) {
+		pr_err("%s: No irq-mapping property in device tree\n", __func__);
+		return -ENODEV;
+	}
+
+    /* Each entry is 2 u32 values: irq + smsm */
+	*count = len / (2 * sizeof(u32));
+
+	*map = kzalloc((*count) * sizeof(**map), GFP_KERNEL);
+	if (!*map) {
+		pr_err("%s: Failed to allocate memory for irq_map\n", __func__);
+		return -ENOMEM;
+	}
+
+	for (i = 0; i < *count; i++) {
+		(*map)[i].irq = be32_to_cpu(prop[i * 2]);
+		(*map)[i].smsm = be32_to_cpu(prop[i * 2 + 1]);
+	}
+
+	return 0;
+}
+
+static int __init msm_init_irq(struct device_node *intc, struct device_node *parent)
+{
+	int ret;
+
+	vic_data.base = of_iomap(intc, 0);
+	if (WARN_ON(!vic_data.base))
+		return -EIO;
+	ret = of_property_read_u32(intc, "num-irqs", &vic_data.nr_vic_irqs);
+	if (ret) {
+		pr_err("%s: failed to read num-irqs ret=%d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = of_property_read_u32(intc, "num-gpio-irqs", &vic_data.nr_gpio_irqs);
+	if (ret) {
+		pr_err("%s: failed to read num-gpio-irqs ret=%d\n", __func__, ret);
+		return ret;
+	}
+
+	ret = msm_vic_parse_irq_mapping(intc, &vic_data.irq_map, &vic_data.irq_map_count);
+	if (ret) {
+		pr_err("Failed to parse irq-mapping\n");
+		return ret;
+	}
+
+	ret = of_property_read_u32(intc, "vic-num-regs", &vic_data.vic_num_regs);
+	if (ret) {
+		pr_err("Failed to parse vic-num-regs\n");
+		return ret;
+	}
+
+	msm_irq_shadow_reg = kcalloc(vic_data.vic_num_regs,
+				     sizeof(*msm_irq_shadow_reg),
+					 GFP_KERNEL);
+
+	msm_irq_idle_disable = kcalloc(vic_data.vic_num_regs,
+				       sizeof(*msm_irq_idle_disable),
+				       GFP_KERNEL);
+
+	if (!msm_irq_shadow_reg || !msm_irq_idle_disable)
+		return -ENOMEM;
+
+	vic_data.msm_nr_irqs = vic_data.nr_vic_irqs * 2 + vic_data.nr_gpio_irqs;
+
+	ret = irq_alloc_descs(-1, 0, vic_data.nr_vic_irqs, 0);
+	if (ret < 0)
+		pr_warn("Couldn't allocate IRQ numbers\n");
+	/* select level interrupts */
+	msm_irq_write_all_regs(vic_data.base + VIC_INT_TYPE0, 0);
+
+	/* select highlevel interrupts */
+	msm_irq_write_all_regs(vic_data.base + VIC_INT_POLARITY0, 0);
+
+	/* select IRQ for all INTs */
+	msm_irq_write_all_regs(vic_data.base + VIC_INT_SELECT0, 0);
+
+	/* disable all INTs */
+	msm_irq_write_all_regs(vic_data.base + VIC_INT_EN0, 0);
+
+	/* don't use vic */
+	writel(0, vic_data.base + VIC_CONFIG);
+
+	/* enable interrupt controller */
+	writel(3, vic_data.base + VIC_INT_MASTEREN);
+
+	for (int n = 0; n < vic_data.msm_nr_irqs; n++) {
+		irq_set_chip_and_handler(n, &msm_irq_chip, handle_level_irq);
+		set_irq_flags(n, IRQF_VALID);
+	}
+
+	/* Ready to receive interrupts */
+	set_handle_irq(vic_handle_irq);
+
+	vic_data.domain = irq_domain_create_legacy
+		(of_fwnode_handle(intc),
+		vic_data.nr_vic_irqs,
+		0, 0,
+		&irq_domain_simple_ops,
+		&vic_data);
+	if (!vic_data.domain)
+		pr_err("%s: failed to register irq domain\n", __func__);
+	return 0;
+}
+
+IRQCHIP_DECLARE(qcom_msm_vic, "qcom,msm-vic", msm_init_irq);
\ No newline at end of file
-- 
2.51.0

Re: [PATCH 2/5] irqchip: Add Qualcomm MSM VIC driver

[Krzysztof Kozlowski]

On 15/03/2026 12:17, j0sh1x wrote:
> Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>

You must use full name.

> ---
>  drivers/irqchip/irq-msm-vic.c | 361 ++++++++++++++++++++++++++++++++++
>  1 file changed, 361 insertions(+)
>  create mode 100644 drivers/irqchip/irq-msm-vic.c
> 
> diff --git a/drivers/irqchip/irq-msm-vic.c b/drivers/irqchip/irq-msm-vic.c
> new file mode 100644
> index 000000000000..7e7f7be3ad6d
> --- /dev/null
> +++ b/drivers/irqchip/irq-msm-vic.c
> @@ -0,0 +1,361 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2007 Google, Inc.
> + * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
> + * Copyright (c) 2024, Htc Leo Revival Project
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.

We don't take 19 years old code. You need to fix it to match current
Linux kernel style, which means most likely all this has to be
completely rewritten from scratch. Take latest reviewed drivers as
starting point, not something from 2007.

Best regards,
Krzysztof

Re: [PATCH 2/5] irqchip: Add Qualcomm MSM VIC driver

[Thomas Gleixner]

On Sun, Mar 15 2026 at 12:17, j0sh1x wrote:

That's a lot of void in this change log. And you have to provide a real
name.

> +++ b/drivers/irqchip/irq-msm-vic.c
> @@ -0,0 +1,361 @@
> +// SPDX-License-Identifier: GPL-2.0 OR MIT
> +/*
> + * Copyright (C) 2007 Google, Inc.
> + * Copyright (c) 2009, Code Aurora Forum. All rights reserved.
> + * Copyright (c) 2024, Htc Leo Revival Project
> + *
> + * This software is licensed under the terms of the GNU General Public
> + * License version 2, as published by the Free Software Foundation, and
> + * may be copied, distributed, and modified under those terms.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.

You have the SPDX license identifier, so no need for the boiler plate.

https://www.kernel.org/doc/Documentation/process/license-rules.rst

> + *
> + */
> +
> +#include <linux/init.h>
> +#include <linux/module.h>
> +#include <linux/sched.h>
> +#include <linux/interrupt.h>
> +#include <linux/ptrace.h>
> +#include <linux/timer.h>
> +#include <linux/irq.h>
> +#include <linux/irqchip.h>
> +#include <linux/io.h>
> +#include <linux/of.h>
> +#include <linux/of_address.h>
> +#include <linux/of_irq.h>
> +#include <linux/of_platform.h>
> +#include <linux/cacheflush.h>

Please order the includes alphabetically and remove all unneeded
ones. There are quite some pointless ones.

> +#include <asm/exception.h>
> +#include <asm/irq.h>
> +
> +#include <dt-bindings/interrupt-controller/qcom-vic.h>
> +
> +static u32 msm_irq_smsm_wake_enable[2];
> +struct msm_irq_shadow {

Please put a new line between the variable and the structure definition.

> +	u32 int_en[2];
> +	u32 int_type;
> +	u32 int_polarity;
> +	u32 int_select;
> +};
> +
> +static struct msm_irq_shadow *msm_irq_shadow_reg;
> +static u32 *msm_irq_idle_disable;
> +
> +struct msm_irq_map {
> +	u32 irq;
> +	u8 smsm;
> +};
> +
> +struct vic_device {
> +	void __iomem *base;
> +	struct irq_domain *domain;
> +	u32				msm_nr_irqs;
> +	u32				nr_vic_irqs;
> +	u32				nr_gpio_irqs;
> +	u32				vic_num_regs;
> +	struct msm_irq_map *irq_map;
> +	int irq_map_count;

https://www.kernel.org/doc/html/latest/process/maintainer-tip.html

Please read and follow it.

> +};
> +
> +static struct vic_device vic_data;

Please have the struct declarations first and then define all the static
variables.

> +static int msm_irq_to_smsm(u32 irq)
> +{
> +	int i;
> +
> +	if (!vic_data.irq_map)
> +		return -EINVAL;
> +
> +	for (i = 0; i < vic_data.irq_map_count; i++) {

  for (int i = 0;

> +		if (vic_data.irq_map[i].irq == irq)
> +			return vic_data.irq_map[i].smsm;
> +		}
> +
> +	return -ENOENT;
> +}
> +
> +void set_irq_flags(unsigned int irq, unsigned int iflags);

What?

> +void set_irq_flags(unsigned int irq, unsigned int iflags)
> +{
> +	unsigned long clr = 0, set = IRQ_NOREQUEST | IRQ_NOPROBE | IRQ_NOAUTOEN;
> +
> +	if (irq >= vic_data.msm_nr_irqs) {
> +		pr_err("Trying to set irq flags for IRQ%d\n", irq);
> +		return;
> +	}
> +
> +	if (iflags & IRQF_VALID)
> +		clr |= IRQ_NOREQUEST;
> +	if (iflags & IRQF_PROBE)
> +		clr |= IRQ_NOPROBE;
> +	if (!(iflags & IRQF_NOAUTOEN))
> +		clr |= IRQ_NOAUTOEN;
> +	/* Order is clear bits in "clr" then set bits in "set" */
> +	irq_modify_status(irq, clr, set & ~clr);
> +}
> +EXPORT_SYMBOL_GPL(set_irq_flags);

Not going to happen. There is existing infrastructure for that and there
is nothing VIC specific about this. set_irq_flags() has been removed
from the kernel long ago for a reason.

> +static inline void msm_irq_write_all_regs(void __iomem *base, unsigned int val)
> +{
> +	for (int i = 0; i < vic_data.vic_num_regs; i++)
> +		writel(val, base + (i * 4));
> +}
> +
> +static void msm_irq_ack(struct irq_data *d)
> +{
> +	void __iomem *reg = VIC_INT_TO_REG_ADDR(vic_data.base + VIC_INT_CLEAR0, d->irq);
> +
> +	writel(1 << (d->irq & 31), reg);
> +}
> +
> +static void msm_irq_mask(struct irq_data *d)
> +{
> +	void __iomem *reg = VIC_INT_TO_REG_ADDR(vic_data.base + VIC_INT_ENCLEAR0, d->irq);
> +	unsigned int index = VIC_INT_TO_REG_INDEX(d->irq);
> +	u32 mask = 1UL << (d->irq & 31);
> +	int smsm_irq = msm_irq_to_smsm(d->irq);

Variable declaration ordering.

> +
> +	msm_irq_shadow_reg[index].int_en[0] &= ~mask;
> +	writel(mask, reg);
> +	if (smsm_irq == 0) {
> +		msm_irq_idle_disable[index] &= ~mask;
> +	} else {
> +		mask = 1UL << (smsm_irq - 1);
> +		msm_irq_smsm_wake_enable[0] &= ~mask;
> +	}
> +}
> +static inline void msm_vic_handle_irq(void __iomem *base_addr, struct pt_regs
> +		*regs)

Bogus line break

> +{
> +	u32 irqnr;
> +
> +	do {
> +		/* VIC_IRQ_VEC_RD has irq# or old irq# if the irq has been handled

Bogus comment style.

> +		 * VIC_IRQ_VEC_PEND_RD has irq# or -1 if none pending *but* if you
> +		 * just read VIC_IRQ_VEC_PEND_RD you never get the first irq for some reason
> +		 */
> +		irqnr = readl_relaxed(base_addr + VIC_IRQ_VEC_RD);
> +		irqnr = readl_relaxed(base_addr + VIC_IRQ_VEC_PEND_RD);
> +		if (irqnr == -1)

-1 on a u32? That's just sloppy. Use a proper define like:

#define NO_PENDING_IRQ	(~0U)

		if (irqnr == NO_PENDING_IRQ)


> +			break;
> +		handle_IRQ(irqnr, regs);
> +	} while (1);
> +}
> +
> +/* enable imprecise aborts */
> +static inline void local_cpsie_enable(void)
> +{
> +	asm volatile("cpsie a" : : : "memory");
> +}
> +
> +static void __exception_irq_entry vic_handle_irq(struct pt_regs *regs)
> +{
> +	local_cpsie_enable();// local_abt_enable()?

No tail comments please.

> +	msm_vic_handle_irq(vic_data.base, regs);
> +}
> +
> +static struct irq_chip msm_irq_chip = {
> +	.name          = "msm",
> +	.irq_disable   = msm_irq_mask,
> +	.irq_ack       = msm_irq_ack,
> +	.irq_mask      = msm_irq_mask,
> +	.irq_unmask    = msm_irq_unmask,
> +	.irq_set_wake  = msm_irq_set_wake,
> +	.irq_set_type  = msm_irq_set_type,
> +};
> +
> +static int msm_vic_parse_irq_mapping(struct device_node *np, struct msm_irq_map **map, int *count)
> +{
> +	const __be32 *prop;
> +	int len, i;
> +
> +	prop = of_get_property(np, "irq-mapping", &len);
> +	if (!prop) {
> +		pr_err("%s: No irq-mapping property in device tree\n", __func__);
> +		return -ENODEV;
> +	}
> +
> +    /* Each entry is 2 u32 values: irq + smsm */
> +	*count = len / (2 * sizeof(u32));
> +
> +	*map = kzalloc((*count) * sizeof(**map), GFP_KERNEL);
> +	if (!*map) {
> +		pr_err("%s: Failed to allocate memory for irq_map\n", __func__);
> +		return -ENOMEM;
> +	}
> +
> +	for (i = 0; i < *count; i++) {
> +		(*map)[i].irq = be32_to_cpu(prop[i * 2]);
> +		(*map)[i].smsm = be32_to_cpu(prop[i * 2 + 1]);
> +	}

Why is anything in the device tree big endian on a little endian system?

Also this code is unreadable and incomprehensible. 

> +
> +	return 0;
> +}
> +
> +static int __init msm_init_irq(struct device_node *intc, struct device_node *parent)
> +{
> +	int ret;
> +
> +	vic_data.base = of_iomap(intc, 0);
> +	if (WARN_ON(!vic_data.base))
> +		return -EIO;
> +	ret = of_property_read_u32(intc, "num-irqs", &vic_data.nr_vic_irqs);
> +	if (ret) {
> +		pr_err("%s: failed to read num-irqs ret=%d\n", __func__, ret);
> +		return ret;
> +	}
> +
> +	ret = of_property_read_u32(intc, "num-gpio-irqs", &vic_data.nr_gpio_irqs);
> +	if (ret) {
> +		pr_err("%s: failed to read num-gpio-irqs ret=%d\n", __func__, ret);
> +		return ret;
> +	}

Read all the required information into local variables first and then
allocate the vic_device data including the mapping table in one go.

> +	msm_irq_shadow_reg = kcalloc(vic_data.vic_num_regs,
> +				     sizeof(*msm_irq_shadow_reg),
> +					 GFP_KERNEL);

You have 100 characters.

> +	msm_irq_idle_disable = kcalloc(vic_data.vic_num_regs,
> +				       sizeof(*msm_irq_idle_disable),
> +				       GFP_KERNEL);
> +
> +	if (!msm_irq_shadow_reg || !msm_irq_idle_disable)
> +		return -ENOMEM;

That leaks the previous allocations.

> +	vic_data.msm_nr_irqs = vic_data.nr_vic_irqs * 2 + vic_data.nr_gpio_irqs;
> +
> +	ret = irq_alloc_descs(-1, 0, vic_data.nr_vic_irqs, 0);

No. That's not how any of this works. A interrupt driver has no business
to allocate interrupt descriptors. Use proper interrupt domains and not
this cobbled together gunk collected from some out of tree garbage can.

There are enough recent examples of properly written interrupt chip
drivers in drivers/irqchip to learn from.

> +IRQCHIP_DECLARE(qcom_msm_vic, "qcom,msm-vic", msm_init_irq);
> \ No newline at end of file

Git gave you a hint right there....

Thanks,

        tglx

[PATCH 3/5] irqchip: Add Kconfig and Makefile entries for MSM VIC

[j0sh1x]

Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>
---
 drivers/irqchip/Kconfig  | 6 ++++++
 drivers/irqchip/Makefile | 1 +
 2 files changed, 7 insertions(+)

diff --git a/drivers/irqchip/Kconfig b/drivers/irqchip/Kconfig
index f07b00d7fef9..84593fff048f 100644
--- a/drivers/irqchip/Kconfig
+++ b/drivers/irqchip/Kconfig
@@ -522,6 +522,12 @@ config QCOM_MPM
 	  MSM Power Manager driver to manage and configure wakeup
 	  IRQs for Qualcomm Technologies Inc (QTI) mobile chips.
 
+config ARM_MSM_VIC
+	tristate "QCOM ARM VIC"
+	select IRQ_DOMAIN
+	help
+	  QCOM Vectored Interrupt Controller driver for MSM platforms.
+
 config CSKY_MPINTC
 	bool
 	depends on CSKY
diff --git a/drivers/irqchip/Makefile b/drivers/irqchip/Makefile
index 26aa3b6ec99f..2acb8929e3b8 100644
--- a/drivers/irqchip/Makefile
+++ b/drivers/irqchip/Makefile
@@ -41,6 +41,7 @@ obj-$(CONFIG_ARM_GIC_V5)		+= irq-gic-v5.o irq-gic-v5-irs.o irq-gic-v5-its.o \
 obj-$(CONFIG_HISILICON_IRQ_MBIGEN)	+= irq-mbigen.o
 obj-$(CONFIG_ARM_NVIC)			+= irq-nvic.o
 obj-$(CONFIG_ARM_VIC)			+= irq-vic.o
+obj-$(CONFIG_ARM_MSM_VIC)			+= irq-msm-vic.o
 obj-$(CONFIG_ARMADA_370_XP_IRQ)		+= irq-armada-370-xp.o
 obj-$(CONFIG_ATMEL_AIC_IRQ)		+= irq-atmel-aic-common.o irq-atmel-aic.o
 obj-$(CONFIG_ATMEL_AIC5_IRQ)	+= irq-atmel-aic-common.o irq-atmel-aic5.o
-- 
2.51.0

[PATCH 4/5] dt-bindings: irq: Add Qualcomm MSM VIC header

[j0sh1x]

Add DT binding constants for the Qualcomm MSM VIC interrupt controller.

These constants are used in the irq-mapping and other driver bindings
to reference specific interrupts and SMSM wakeup channels.

Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>
---
 .../interrupt-controller/qcom-vic.h           | 92 +++++++++++++++++++
 1 file changed, 92 insertions(+)
 create mode 100644 include/dt-bindings/interrupt-controller/qcom-vic.h

diff --git a/include/dt-bindings/interrupt-controller/qcom-vic.h b/include/dt-bindings/interrupt-controller/qcom-vic.h
new file mode 100644
index 000000000000..8fbcf8f61103
--- /dev/null
+++ b/include/dt-bindings/interrupt-controller/qcom-vic.h
@@ -0,0 +1,92 @@
+/* SPDX-License-Identifier: GPL-2.0 OR MIT */
+/*
+ * This header provides constants for the ARM GIC.
+ */
+
+#ifndef _DT_BINDINGS_INTERRUPT_CONTROLLER_QCOM_VIC_H
+#define _DT_BINDINGS_INTERRUPT_CONTROLLER_QCOM_VIC_H
+
+#include <dt-bindings/interrupt-controller/irq.h>
+
+#define VIC_INT_TO_REG_ADDR(base, irq) (base + ((irq & 32) ? 4 : 0))
+#define VIC_INT_TO_REG_INDEX(irq) ((irq >> 5) & 1)
+
+#define VIC_INT_SELECT0     0x0000  /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT1     0x0004  /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT2     0x0008  /* 1: FIQ, 0: IRQ */
+#define VIC_INT_SELECT3     0x000C  /* 1: FIQ, 0: IRQ */
+#define VIC_INT_EN0         0x0010
+#define VIC_INT_EN1         0x0014
+#define VIC_INT_EN2         0x0018
+#define VIC_INT_EN3         0x001C
+#define VIC_INT_ENCLEAR0    0x0020
+#define VIC_INT_ENCLEAR1    0x0024
+#define VIC_INT_ENCLEAR2    0x0028
+#define VIC_INT_ENCLEAR3    0x002C
+#define VIC_INT_ENSET0      0x0030
+#define VIC_INT_ENSET1      0x0034
+#define VIC_INT_ENSET2      0x0038
+#define VIC_INT_ENSET3      0x003C
+#define VIC_INT_TYPE0       0x0040  /* 1: EDGE, 0: LEVEL  */
+#define VIC_INT_TYPE1       0x0044  /* 1: EDGE, 0: LEVEL  */
+#define VIC_INT_TYPE2       0x0048  /* 1: EDGE, 0: LEVEL  */
+#define VIC_INT_TYPE3       0x004C  /* 1: EDGE, 0: LEVEL  */
+#define VIC_INT_POLARITY0   0x0050  /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY1   0x0054  /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY2   0x0058  /* 1: NEG, 0: POS */
+#define VIC_INT_POLARITY3   0x005C  /* 1: NEG, 0: POS */
+#define VIC_NO_PEND_VAL     0x0060
+
+
+#define VIC_NO_PEND_VAL_FIQ 0x0064
+#define VIC_INT_MASTEREN    0x0068  /* 1: IRQ, 2: FIQ     */
+#define VIC_CONFIG          0x006C  /* 1: USE SC VIC */
+
+
+#define IRQF_VALID	(1 << 0)
+#define IRQF_PROBE	(1 << 1)
+#define IRQF_NOAUTOEN	(1 << 2)
+
+#define VIC_IRQ_STATUS0     0x0080
+#define VIC_IRQ_STATUS1     0x0084
+#define VIC_IRQ_STATUS2     0x0088
+#define VIC_IRQ_STATUS3     0x008C
+#define VIC_FIQ_STATUS0     0x0090
+#define VIC_FIQ_STATUS1     0x0094
+#define VIC_FIQ_STATUS2     0x0098
+#define VIC_FIQ_STATUS3     0x009C
+#define VIC_RAW_STATUS0     0x00A0
+#define VIC_RAW_STATUS1     0x00A4
+#define VIC_RAW_STATUS2     0x00A8
+#define VIC_RAW_STATUS3     0x00AC
+#define VIC_INT_CLEAR0      0x00B0
+#define VIC_INT_CLEAR1      0x00B4
+#define VIC_INT_CLEAR2      0x00B8
+#define VIC_INT_CLEAR3      0x00BC
+#define VIC_SOFTINT0        0x00C0
+#define VIC_SOFTINT1        0x00C4
+#define VIC_SOFTINT2        0x00C8
+#define VIC_SOFTINT3        0x00CC
+#define VIC_IRQ_VEC_RD      0x00D0  /* pending int # */
+#define VIC_IRQ_VEC_PEND_RD 0x00D4  /* pending vector addr */
+#define VIC_IRQ_VEC_WR      0x00D8
+
+
+#define VIC_FIQ_VEC_RD      0x00DC
+#define VIC_FIQ_VEC_PEND_RD 0x00E0
+#define VIC_FIQ_VEC_WR      0x00E4
+#define VIC_IRQ_IN_SERVICE  0x00E8
+#define VIC_IRQ_IN_STACK    0x00EC
+#define VIC_FIQ_IN_SERVICE  0x00F0
+#define VIC_FIQ_IN_STACK    0x00F4
+#define VIC_TEST_BUS_SEL    0x00F8
+#define VIC_IRQ_CTRL_CONFIG 0x00FC
+
+
+#define VIC_VECTPRIORITY(n) 0x0200+((n) * 4)
+#define VIC_VECTADDR(n)     0x0400+((n) * 4)
+
+#define SMSM_FAKE_IRQ (0xff)
+
+#define VIC_NUM_REGS	    2
+#endif
-- 
2.51.0

Re: [PATCH 4/5] dt-bindings: irq: Add Qualcomm MSM VIC header

[Krzysztof Kozlowski]

On 15/03/2026 12:17, j0sh1x wrote:
> Add DT binding constants for the Qualcomm MSM VIC interrupt controller.
> 
> These constants are used in the irq-mapping and other driver bindings
> to reference specific interrupts and SMSM wakeup channels.
> 
> Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>
> ---
>  .../interrupt-controller/qcom-vic.h           | 92 +++++++++++++++++++

No, not a binding. Don't add such stuff.

Best regards,
Krzysztof

[PATCH 5/5] MAINTAINERS: Add Maintainer entry for MSM VIC

[j0sh1x]

Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>
---
 MAINTAINERS | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/MAINTAINERS b/MAINTAINERS
index 96ea84948d76..b331d3d69b12 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -21890,6 +21890,12 @@ S:	Supported
 W:	https://wireless.wiki.kernel.org/en/users/Drivers/wcn36xx
 F:	drivers/net/wireless/ath/wcn36xx/
 
+QUALCOMM VECTORED INTERRUPT CONTROLLER (VIC) DRIVER
+M:	j0sh1x <aljoshua.hell@gmail.com>
+S:	Maintained
+F:	Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml
+F:	drivers/irqchip/irq-msm-vic.c
+
 QUANTENNA QTNFMAC WIRELESS DRIVER
 M:	Igor Mitsyanko <imitsyanko@quantenna.com>
 R:	Sergey Matyukevich <geomatsi@gmail.com>
-- 
2.51.0

Re: [PATCH 1/5] dt-bindings: irq: Add Qualcomm MSM VIC binding

[Krzysztof Kozlowski]

On 15/03/2026 12:17, j0sh1x wrote:
> Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>

Please run scripts/checkpatch.pl on the patches and fix reported
warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
patches and (probably) fix more warnings. Some warnings can be ignored,
especially from --strict run, but the code here looks like it needs a
fix. Feel free to get in touch if the warning is not clear.

Please use scripts/get_maintainers.pl to get a list of necessary people
and lists to CC. It might happen, that command when run on an older
kernel, gives you outdated entries. Therefore please be sure you base
your patches on recent Linux kernel.

Tools like b4 or scripts/get_maintainer.pl provide you proper list of
people, so fix your workflow. Tools might also fail if you work on some
ancient tree (don't, instead use mainline) or work on fork of kernel
(don't, instead use mainline). Just use b4 and everything should be
fine, although remember about `b4 prep --auto-to-cc` if you added new
patches to the patchset.

You missed at least devicetree list (maybe more), so this won't be
tested by automated tooling. Performing review on untested code might be
a waste of time.

Please kindly resend and include all necessary To/Cc entries.

> ---
>  .../interrupt-controller/qcom,msm-vic.yaml    | 72 +++++++++++++++++++
>  1 file changed, 72 insertions(+)
>  create mode 100644 Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml
> 
> diff --git a/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml b/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml
> new file mode 100644
> index 000000000000..5bf281f72fe0
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interrupt-controller/qcom,msm-vic.yaml
> @@ -0,0 +1,72 @@
> +# SPDX-License-Identifier: GPL-2.0
> +# qualcomm,msm-vic.yaml - Device Tree binding for Qualcomm MSM VIC interrupt controller
> +
> +description: >
> +  Qualcomm MSM VIC (Vector Interrupt Controller). This interrupt controller
> +  handles normal and wakeup interrupts and supports mapping to the
> +  Qualcomm SMSM system.
> +
> +compatible: ["qcom,msm-vic"]
> +
> +properties:
> +  interrupt-controller:
> +    description: "Identifies this node as an interrupt controller"
> +    required: true
> +    type: boolean
> +
> +  #interrupt-cells:
> +    description: "Specifies the number of cells needed to encode an interrupt"
> +    required: true
> +    type: integer
> +    default: 1

I don't know what you wrote, but this is not a DT binding. Don't send us
LLM microslop products. Read first docs guiding you what you have to do.

Also, nothing here was tested.

NAK

Best regards,
Krzysztof

Re: [PATCH 1/5] dt-bindings: irq: Add Qualcomm MSM VIC binding

[Krzysztof Kozlowski]

On 16/03/2026 09:29, Krzysztof Kozlowski wrote:
> On 15/03/2026 12:17, j0sh1x wrote:
>> Signed-off-by: j0sh1x <aljoshua.hell@gmail.com>
> 
> Please run scripts/checkpatch.pl on the patches and fix reported
> warnings. After that, run also 'scripts/checkpatch.pl --strict' on the
> patches and (probably) fix more warnings. Some warnings can be ignored,
> especially from --strict run, but the code here looks like it needs a
> fix. Feel free to get in touch if the warning is not clear.
> 
> Please use scripts/get_maintainers.pl to get a list of necessary people
> and lists to CC. It might happen, that command when run on an older
> kernel, gives you outdated entries. Therefore please be sure you base
> your patches on recent Linux kernel.
> 
> Tools like b4 or scripts/get_maintainer.pl provide you proper list of
> people, so fix your workflow. Tools might also fail if you work on some
> ancient tree (don't, instead use mainline) or work on fork of kernel
> (don't, instead use mainline). Just use b4 and everything should be
> fine, although remember about `b4 prep --auto-to-cc` if you added new
> patches to the patchset.
> 
> You missed at least devicetree list (maybe more), so this won't be
> tested by automated tooling. Performing review on untested code might be
> a waste of time.
> 
> Please kindly resend and include all necessary To/Cc entries.
> 

Also, please go through comments here:
https://sashiko.dev/#/patchset/20260315111705.118544-1-aljoshua.hell%40gmail.com

At least the one about header was kind of right:

"Headers in include/dt-bindings/ are typically meant to define the
stable ABI between device tree sources and the OS. Exposing internal
hardware register offsets and software flags here might pollute the
globally visible DT namespace."

Best regards,
Krzysztof