From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from smtp.kernel.org (aws-us-west-2-korg-mail-1.web.codeaurora.org [10.30.226.201]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 5708E188713 for ; Thu, 3 Apr 2025 17:59:44 +0000 (UTC) Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.client-ip=10.30.226.201 ARC-Seal:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743703185; cv=none; b=B3hoa1fyzo0QG22PXqlYKD6+LzM0TrUUcm44adJRbjTEKUxmhuq25Tb0OsZzVmIsDMx+nznV1v1Qov9XAtqbT3UgE8iR1BG2lmtFcaIu52uI6zqwqL+NmVQEMZ29frI5+jrs2h9q7QE+FKH6Xr9cgfw1W9fJWdLOguycoyo0LlM= ARC-Message-Signature:i=1; a=rsa-sha256; d=subspace.kernel.org; s=arc-20240116; t=1743703185; c=relaxed/simple; bh=u4uBLvKcZDtXzM4whjtNyxhNgE6BnlY7nR+h63ZqcD8=; h=Date:Message-ID:From:To:Cc:Subject:In-Reply-To:References: MIME-Version:Content-Type; b=WeiW5luVFuZh0+WgtXEQh85rKpjCX9yuPMPvNnlgcfgv6v+hfBziqzj2TLgYs8nxLOVj6vgVbfe/F0W/Pi2TB8DJ2nKYnfG6QMWzMI/I/4zi3N2ItI7EW9GQRtbBXc6ITvNX8Bd/MREeytnYfkA5r3pb988vAcWU7AT721zJPMw= ARC-Authentication-Results:i=1; smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b=G0Qmmlyi; arc=none smtp.client-ip=10.30.226.201 Authentication-Results: smtp.subspace.kernel.org; dkim=pass (2048-bit key) header.d=kernel.org header.i=@kernel.org header.b="G0Qmmlyi" Received: by smtp.kernel.org (Postfix) with ESMTPSA id 9765DC4CEE3; Thu, 3 Apr 2025 17:59:44 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1743703184; bh=u4uBLvKcZDtXzM4whjtNyxhNgE6BnlY7nR+h63ZqcD8=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=G0Qmmlyigjizi2H/AnHP4w56K7NJ7gb9sO5WSVqeefPCtJqwGMvsY87S1d7RCNVSg Ia8u9mQXOR+06aESkVHsnMxyePthINhCAxYXHvtYj9ZWQ583ltgJnfI37gwg+yG+hw bv0T2MoUXNWYCaQ5mdp3+xeP8/UEDkfvOu7c4myR5xHy9KptzsinjE0Hoqspuis5DC mDpvIRl0DsolBk0e1F/d92DMll5lziPIQLorIZfUQ9TqHW5fQxgnTAJzbGaj85jKsX W8S7OYrOMWVmg7/eMLzmXfS3Zg07ogF9FNDjp/e4lMMdCTfCLabJkb66/QmBO4YDV2 av2HP0RewHNIw== Received: from sofa.misterjones.org ([185.219.108.64] helo=lobster-girl.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1u0Oqs-0022UN-8c; Thu, 03 Apr 2025 18:59:42 +0100 Date: Thu, 03 Apr 2025 18:59:44 +0100 Message-ID: <871pu9yvlb.wl-maz@kernel.org> From: Marc Zyngier To: Breno Leitao Cc: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, arnd@arndb.de, kernel-team@meta.com, vincenzo.frascino@arm.com, anders.roxell@linaro.org, ndecarli@meta.com, rmikey@meta.com Subject: Re: [PATCH RFC] arm64: vdso: Use __arch_counter_get_cntvct() In-Reply-To: References: <20250402-arm-vdso-v1-1-2e7a12d75107@debian.org> <87a58yz0cm.wl-maz@kernel.org> <878qoiyzic.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/30.1 (aarch64-unknown-linux-gnu) MULE/6.0 (HANACHIRUSATO) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: leitao@debian.org, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, arnd@arndb.de, kernel-team@meta.com, vincenzo.frascino@arm.com, anders.roxell@linaro.org, ndecarli@meta.com, rmikey@meta.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false On Thu, 03 Apr 2025 13:14:49 +0100, Breno Leitao wrote: > > Since you created *all* this noise regarding instruction ordering, can > I pick your brain in the same topic? :-P > > If my machine has Speculation Barrier (sb)[1] support, is it a good > replacement for `isb` ? Do you happen to know? Probably not. SB prevent speculation past it, while ISB is here to enforce ordering. We're pretty happy to let the CPU speculate the counter, as long as it does it the order we have defined. On some implementation, this can be have a similar effect (drain the fetch queue, restart). But the intent clearly isn't the same, and some implementations may do things differently. In any case, what you want is CNTVCTSS_EL0 (part of FEAT_ECV), which does away with all barriers. M. -- Jazz isn't dead. It just smells funny.