From: Thomas Gleixner <tglx@linutronix.de>
To: "Chang S. Bae" <chang.seok.bae@intel.com>,
Borislav Petkov <bp@alien8.de>
Cc: linux-kernel@vger.kernel.org, x86@kernel.org, mingo@redhat.com,
dave.hansen@linux.intel.com
Subject: Re: [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging
Date: Thu, 07 Nov 2024 02:12:46 +0100 [thread overview]
Message-ID: <871pznq229.ffs@tglx> (raw)
In-Reply-To: <d8d3959a-8c38-4ce4-885d-6a1e40219831@intel.com>
On Wed, Nov 06 2024 at 10:28, Chang S. Bae wrote:
> On 11/4/2024 3:16 AM, Borislav Petkov wrote:
>> On Tue, Oct 01, 2024 at 09:10:39AM -0700, Chang S. Bae wrote:
>>> +
>>> +static bool need_staging(u64 *mmio_addrs, u64 pa)
>>> +{
>>> + unsigned int i;
>>> +
>>> + for (i = 0; mmio_addrs[i] != 0; i++) {
>>> + if (mmio_addrs[i] == pa)
>>> + return false;
>>> + }
>>> + mmio_addrs[i] = pa;
>>
>> This is a weird function - its name is supposed to mean it queries something
>> but then it has side effects too.
>
> I think I've carved out a bit more out of the loop and convoluted them
> into a single function.
>
> Instead, let the helper simply find the position in the array,
>
> static unsigned int find_pos(u64 *mmio_addrs, u64 mmio_pa)
> {
> unsigned int i;
>
> for (i = 0; mmio_addrs[i] != 0; i++) {
> if (mmio_addrs[i] == mmio_pa)
> break;
> }
> return i;
> }
>
> and update the array from there:
>
> static void stage_microcode(void)
> {
> unsigned int pos;
> ...
> for_each_cpu(cpu, cpu_online_mask) {
> /* set 'mmio_pa' from RDMSR */
>
> pos = find_pos(mmio_addrs, mmio_pa);
> if (mmio_addrs[pos] == mmio_pa)
> continue;
>
> /* do staging */
>
> mmio_addrs[pos] = mmio_pa;
> }
> ...
> }
>
> Or, even the loop code can include it:
>
> for_each_cpu(...) {
> /* set 'mmio_pa' from RDMSR */
>
> /* Find either the last position or a match */
> for (i = 0; mmio_addrs[i] != 0 && mmio_addrs[i] !=
> mmio_pa; i++);
>
> if (mmio_addrs[i] == mmio_pa)
> continue;
>
> /* do staging */
>
> mmio_addrs[i] = mmio_pa;
> }
This looks all overly complicated. The documentation says:
"There is one set of mailbox registers and internal staging buffers per
physical processor package. Therefore, the IA32_MCU_STAGING_MBOX_ADDR
MSR is package-scoped and will provide a different physical address on
each physical package."
So why going through loops and hoops?
pkg_id = UINT_MAX;
for_each_online_cpu(cpu) {
if (topology_logical_package_id(cpu) == pkg_id)
continue;
pkg_id = topology_logical_package_id(cpu);
rdmsrl_on_cpu(cpu, MSR_IA32_MCU_STAGING_MBOX_ADDR, &pa);
staging_work(pa, ucode_patch_late, totalsize);
}
Something like that should just work, no?
Thanks,
tglx
next prev parent reply other threads:[~2024-11-07 1:12 UTC|newest]
Thread overview: 44+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-10-01 16:10 [PATCH RFC 0/7] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 1/7] x86/microcode/intel: Remove unnecessary cache writeback and invalidation Chang S. Bae
2024-10-25 16:24 ` [tip: x86/microcode] " tip-bot2 for Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 2/7] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2024-11-04 10:45 ` Borislav Petkov
2024-10-01 16:10 ` [PATCH RFC 3/7] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-04 11:16 ` Borislav Petkov
2024-11-04 16:08 ` Dave Hansen
2024-11-04 18:34 ` Chang S. Bae
2024-11-04 20:10 ` Chang S. Bae
2024-11-06 18:23 ` [PATCH] cpufreq: Simplify MSR read on the boot CPU Chang S. Bae
2024-11-12 20:44 ` Rafael J. Wysocki
2024-11-06 18:28 ` [PATCH RFC 4/7] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2024-11-07 1:12 ` Thomas Gleixner [this message]
2024-11-08 22:42 ` Chang S. Bae
2024-11-08 22:51 ` Dave Hansen
2024-10-01 16:10 ` [PATCH RFC 5/7] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 6/7] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2024-10-01 16:10 ` [PATCH RFC 7/7] x86/microcode/intel: Enable staging when available Chang S. Bae
2024-12-11 1:42 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2024-12-11 1:42 ` [PATCH 1/6] x86/microcode: Introduce staging option to reduce late-loading latency Chang S. Bae
2025-02-17 13:33 ` Borislav Petkov
2025-02-18 7:51 ` Chang S. Bae
2025-02-18 11:36 ` Borislav Petkov
2025-02-18 15:16 ` Dave Hansen
2024-12-11 1:42 ` [PATCH 2/6] x86/msr-index: Define MSR index and bit for the microcode staging feature Chang S. Bae
2025-02-26 17:19 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 3/6] x86/microcode/intel: Prepare for microcode staging Chang S. Bae
2025-02-26 17:52 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 4/6] x86/microcode/intel_staging: Implement staging logic Chang S. Bae
2025-02-18 20:16 ` Dave Hansen
2025-02-26 17:56 ` Borislav Petkov
2024-12-11 1:42 ` [PATCH 5/6] x86/microcode/intel_staging: Support mailbox data transfer Chang S. Bae
2025-02-18 20:54 ` Dave Hansen
2025-03-20 23:42 ` Chang S. Bae
2024-12-11 1:42 ` [PATCH 6/6] x86/microcode/intel: Enable staging when available Chang S. Bae
2025-02-07 18:37 ` [PATCH 0/6] x86/microcode: Support for Intel Staging Feature Chang S. Bae
2025-02-28 22:27 ` Colin Mitchell
2025-02-28 22:52 ` Borislav Petkov
2025-02-28 23:23 ` Dave Hansen
2025-03-26 21:29 ` Colin Mitchell
2025-04-02 17:14 ` Dave Hansen
2025-02-28 23:05 ` Dave Hansen
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