From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 3E5D6C433F5 for ; Wed, 17 Nov 2021 09:13:49 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 231CD6137E for ; Wed, 17 Nov 2021 09:13:49 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S234863AbhKQJQi (ORCPT ); Wed, 17 Nov 2021 04:16:38 -0500 Received: from mail.kernel.org ([198.145.29.99]:53652 "EHLO mail.kernel.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S234864AbhKQJQ3 (ORCPT ); Wed, 17 Nov 2021 04:16:29 -0500 Received: from disco-boy.misterjones.org (disco-boy.misterjones.org [51.254.78.96]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by mail.kernel.org (Postfix) with ESMTPSA id 32E2563214; Wed, 17 Nov 2021 09:13:31 +0000 (UTC) Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.94.2) (envelope-from ) id 1mnH0T-00624e-5Z; Wed, 17 Nov 2021 09:13:29 +0000 Date: Wed, 17 Nov 2021 09:13:28 +0000 Message-ID: <871r3f87rb.wl-maz@kernel.org> From: Marc Zyngier To: Dmitry Baryshkov Cc: Catalin Marinas , Will Deacon , linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH] arm64: cpufeature: fix CPU features mismatch message In-Reply-To: <20211116215922.2021550-1-dmitry.baryshkov@linaro.org> References: <20211116215922.2021550-1-dmitry.baryshkov@linaro.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: dmitry.baryshkov@linaro.org, catalin.marinas@arm.com, will@kernel.org, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-kernel@vger.kernel.org On Tue, 16 Nov 2021 21:59:22 +0000, Dmitry Baryshkov wrote: > > Fix cpp magic involved in ARM64_FTR_REG/ARM64_FTR_REG_OVERRIDE macros. > Currently ARM64_FTR_REG parameters are expanded early, resulting in > cryptic debug messages: > > [ 0.071123] CPU features: SANITY CHECK: Unexpected variation in (((3) << 19) | ((0) << 16) | ((0) << 12) | ((7) << 8) | ((0) << 5)). Boot CPU: 0x00022200101022, CPU4: 0x00022200101122 > > Make ARM64_FTR_REG to be expanded before parameters, resulting in proper > debug log: > > [ 0.071163] CPU features: SANITY CHECK: Unexpected variation in SYS_ID_AA64MMFR0_EL1. Boot CPU: 0x00022200101022, CPU4: 0x00022200101122 > > Fixes: 8f266a5d878a ("arm64: cpufeature: Add global feature override facility") > Signed-off-by: Dmitry Baryshkov > --- > arch/arm64/kernel/cpufeature.c | 8 +++++--- > 1 file changed, 5 insertions(+), 3 deletions(-) > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > index 6ec7036ef7e1..72e3e3819eb4 100644 > --- a/arch/arm64/kernel/cpufeature.c > +++ b/arch/arm64/kernel/cpufeature.c > @@ -573,15 +573,17 @@ static const struct arm64_ftr_bits ftr_raz[] = { > ARM64_FTR_END, > }; > > -#define ARM64_FTR_REG_OVERRIDE(id, table, ovr) { \ > +#define __ARM64_FTR_REG(id, _name, table, ovr) { \ > .sys_id = id, \ > .reg = &(struct arm64_ftr_reg){ \ > - .name = #id, \ > + .name = _name, \ > .override = (ovr), \ > .ftr_bits = &((table)[0]), \ > }} > > -#define ARM64_FTR_REG(id, table) ARM64_FTR_REG_OVERRIDE(id, table, &no_override) > +#define ARM64_FTR_REG_OVERRIDE(id, table, ovr) __ARM64_FTR_REG(id, #id, table, ovr) > + > +#define ARM64_FTR_REG(id, table) __ARM64_FTR_REG(id, #id, table, &no_override) > > struct arm64_ftr_override __ro_after_init id_aa64mmfr1_override; > struct arm64_ftr_override __ro_after_init id_aa64pfr1_override; Please see commit 9dc232a8ab18 ("arm64: arm64_ftr_reg->name may not be a human-readable string"). M. -- Without deviation from the norm, progress is not possible.