From: Miquel Raynal <miquel.raynal@bootlin.com>
To: Krzysztof Kozlowski <krzk@kernel.org>
Cc: "Mark Brown" <broonie@kernel.org>,
"Rob Herring" <robh@kernel.org>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
"Conor Dooley" <conor+dt@kernel.org>,
"Geert Uytterhoeven" <geert+renesas@glider.be>,
"Magnus Damm" <magnus.damm@gmail.com>,
"Vaishnav Achath" <vaishnav.a@ti.com>,
"Thomas Petazzoni" <thomas.petazzoni@bootlin.com>,
"Hervé Codina" <herve.codina@bootlin.com>,
"Wolfram Sang" <wsa+renesas@sang-engineering.com>,
"Vignesh Raghavendra" <vigneshr@ti.com>,
"Santhosh Kumar K" <s-k6@ti.com>,
"Pratyush Yadav" <pratyush@kernel.org>,
"Pascal Eberhard" <pascal.eberhard@se.com>,
linux-spi@vger.kernel.org, devicetree@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-renesas-soc@vger.kernel.org
Subject: Re: [PATCH 01/13] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list
Date: Wed, 14 Jan 2026 16:14:40 +0100 [thread overview]
Message-ID: <873448w7j3.fsf@bootlin.com> (raw)
In-Reply-To: <20251220-sexy-feathered-gorilla-3a6aab@quoll> (Krzysztof Kozlowski's message of "Sat, 20 Dec 2025 10:35:56 +0100")
On 20/12/2025 at 10:35:56 +01, Krzysztof Kozlowski <krzk@kernel.org> wrote:
> On Fri, Dec 19, 2025 at 08:22:03PM +0100, Miquel Raynal (Schneider Electric) wrote:
>> Add support for the Renesas RZ/N1D400 QSPI controller.
>>
>> This SoC is identified in the bindings with its other name: r9a06g032.
>> It is part of the RZ/N1 family, which contains a "D" and a "S"
>> variant. Align the compatibles used with all other IPs from the same
>
> I don't get it. I see only one front compatible, so what is exactly
> aligned?
Sorry, indeed the sentence isn't clear. The Cadence QSPI IP is usually
described using two compatibles, and the second is cdns,qspi-nor.
The way that has been historically used to describe RZ/N1D IPs, however,
is to use 3 compatibles. I wanted to "align" with this, ie. declaring 3
strings instead of 2.
I will change the commit log to:
This SoC is identified in the bindings with its other name: r9a06g032.
It is part of the RZ/N1 family, which contains a "D" and a "S"
variant. IPs in this SoC are typically described using 3
compatibles (the SoC specific compatible, the family compatible, and
the original Cadence IP compatible), follow this convention.
I hope this is clearer.
Thanks,
Miquèl
next prev parent reply other threads:[~2026-01-14 15:14 UTC|newest]
Thread overview: 27+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-12-19 19:22 [PATCH 00/13] spi: cadence-qspi: Add Renesas RZ/N1 support Miquel Raynal (Schneider Electric)
2025-12-19 19:22 ` [PATCH 01/13] spi: dt-bindings: cdns,qspi-nor: Add Renesas RZ/N1D400 to the list Miquel Raynal (Schneider Electric)
2025-12-20 9:35 ` Krzysztof Kozlowski
2025-12-20 10:13 ` Wolfram Sang
2026-01-14 14:57 ` Miquel Raynal
2026-01-14 15:14 ` Miquel Raynal [this message]
2025-12-19 19:22 ` [PATCH 02/13] spi: cadence-qspi: Align definitions Miquel Raynal (Schneider Electric)
2025-12-23 14:18 ` Pratyush Yadav
2025-12-19 19:22 ` [PATCH 03/13] spi: cadence-qspi: Fix style and improve readability Miquel Raynal (Schneider Electric)
2025-12-23 14:28 ` Pratyush Yadav
2026-01-14 16:07 ` Miquel Raynal
2025-12-19 19:22 ` [PATCH 04/13] spi: cadence-qspi: Fix ORing style and alignments Miquel Raynal (Schneider Electric)
2025-12-23 14:29 ` Pratyush Yadav
2025-12-19 19:22 ` [PATCH 05/13] spi: cadence-qspi: Remove an useless operation Miquel Raynal (Schneider Electric)
2025-12-23 14:32 ` Pratyush Yadav
2025-12-19 19:22 ` [PATCH 06/13] spi: cadence-qspi: Make sure we filter out unsupported ops Miquel Raynal
2025-12-23 14:33 ` Pratyush Yadav
2025-12-19 19:22 ` [PATCH 07/13] spi: cadence-qspi: Fix probe error path and remove Miquel Raynal (Schneider Electric)
2025-12-22 12:48 ` Geert Uytterhoeven
2026-01-14 14:36 ` Miquel Raynal
2025-12-19 19:22 ` [PATCH 08/13] spi: cadence-qspi: Try hard to disable the clocks Miquel Raynal (Schneider Electric)
2025-12-19 19:22 ` [PATCH 09/13] spi: cadence-qspi: Kill cqspi_jh7110_clk_init Miquel Raynal (Schneider Electric)
2025-12-19 19:22 ` [PATCH 10/13] spi: cadence-qspi: Add a flag for controllers without indirect access support Miquel Raynal (Schneider Electric)
2025-12-19 19:22 ` [PATCH 11/13] spi: cadence-qspi: Make sure write protection is disabled Miquel Raynal (Schneider Electric)
2025-12-19 19:22 ` [PATCH 12/13] spi: cadence-qspi: Add support for the Renesas RZ/N1 controller Miquel Raynal (Schneider Electric)
2025-12-19 19:22 ` [PATCH 13/13] ARM: dts: r9a06g032: Describe the QSPI controller Miquel Raynal (Schneider Electric)
2025-12-20 9:36 ` Krzysztof Kozlowski
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