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From: Thomas Gleixner <tglx@linutronix.de>
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To: Charles Mirabile <cmirabil@redhat.com>, lkp@intel.com
Cc: cmirabil@redhat.com, linux-kernel@vger.kernel.org, lzampier@redhat.com,
 oe-kbuild-all@lists.linux.dev, x86@kernel.org
Subject: Re: [tip:irq/drivers 22/22]
 drivers/irqchip/irq-sifive-plic.c:590:55: sparse: sparse: incorrect type
 in argument 1 (different address spaces)
In-Reply-To: <20251027174725.1014197-1-cmirabil@redhat.com>
References: <202510271316.AQM7gCCy-lkp@intel.com>
 <20251027174725.1014197-1-cmirabil@redhat.com>
Date: Fri, 31 Oct 2025 22:32:52 +0100
Message-ID: <87346ysqnv.ffs@tglx>
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On Mon, Oct 27 2025 at 13:47, Charles Mirabile wrote:
> diff --git a/drivers/irqchip/irq-sifive-plic.c b/drivers/irqchip/irq-sifive-plic.c
> index 9c4af7d58846..fbf7378899d3 100644
> --- a/drivers/irqchip/irq-sifive-plic.c
> +++ b/drivers/irqchip/irq-sifive-plic.c
> @@ -590,12 +590,12 @@ static int plic_probe(struct fwnode_handle *fwnode)
>  		if (parent_hwirq != RV_IRQ_EXT) {
>  			/* Disable S-mode enable bits if running in M-mode. */
>  			if (IS_ENABLED(CONFIG_RISCV_M_MODE)) {
> -				void __iomem *enable_base = priv->regs +
> +				u32 __iomem *enable_base = priv->regs +
>  					CONTEXT_ENABLE_BASE +
>  					i * CONTEXT_ENABLE_SIZE;
>  
> -				for (hwirq = 1; hwirq <= nr_irqs; hwirq++)
> -					__plic_toggle(enable_base, hwirq, 0);
> +				for (int j = 0; j <= nr_irqs / 32; j++)
> +					writel(0, enable_base + j);
>  			}
>  			continue;
>  		}

Care to send a proper patch for that?